Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2006-11-07
2006-11-07
Du, Thuan (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S501000, C713S503000
Reexamination Certificate
active
07134033
ABSTRACT:
A clock-synchronizing apparatus and method of devices with different clocks are disclosed. Between a first device operated with a first clock and a second device operated with a second clock faster than the first clock, an operation latency of the second device refers to the first clock, control signals that controls the second device are generated at the second clock speed according to the operation latency, and an enable interval of the control signals has a 1/4 clock period of the first clock. Accordingly, since the first device and the second device can transmit and receive a data to and from each other while being operated by using their own clock, an access latency for the first device to access the second device can be reduced and a transmission band width between the two devices can be effectively used.
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Heinz Wrobel, Motorola GmbH, Munich and Janet Snyder, NCSD Applications, Austin. AN2066/D MPC8xx SDRAM Interface, Nov. 2001; pp. 1-6.
Du Thuan
Fleshner & Kim LLP
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