Clock skew modelling using delay stamping

Details Clock skew modelling using delay stamping Clock skew modelling using delay stamping

2008-01-29

2008-01-29

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07325211

ABSTRACT:
A method for determining clock skew to avoid hold time violations is provided. The method includes obtaining a total delay to a source by adding a first delay associated with each of the delay elements in a clock tree path leading to a source. The method also includes obtaining a total delay to a destination by adding a second delay associated with each delay element in a clock tree path leading to a destination. Thereafter, a source sum delay of the delay elements in the clock tree path leading from the source to a common point is obtained. Similarly, a destination sum delay is obtained for the delay elements in the clock tree path from the destination to the common point. Subsequently, the actual delay to the source is obtained by subtracting the source sum delay from the total delay. Similarly, actual delay to the destination is obtained by subtracting the destination sum delay from the total delay. The skew value is then calculated by subtracting the actual delay to the source from the actual delay to the destination.

REFERENCES:
patent: 6550044 (2003-04-01), Pavisic et al.
patent: 7039891 (2006-05-01), Tetelbaum
patent: 7096442 (2006-08-01), Lu et al.
patent: 2005/0050497 (2005-03-01), Tetelbaum
patent: 2005/0268263 (2005-12-01), Sun et al.
patent: 2006/0010408 (2006-01-01), Auracher et al.

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