Clock signal latency elimination network

Details Clock signal latency elimination network Clock signal latency elimination network

1991-09-20

1993-12-21

Kuntz, Curtis

Pulse or digital communications

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371 1, 307269, 307511, 328 63, 328155, H04L 700, H04L 2536, H04L 2540

Patent

active

052727297

ABSTRACT:
A process independent digital clock signal timing network is described for generating a chip clock substantially in phase with and offset by one cycle from an input clock signal. The timing network determines the delay experienced by a clock signal passing through a predetermined internal clock circuit on the chip and pregates the internal clock circuit by an amount equivalent to the determined delay such that the chip clock signal output from the internal clock circuitry lags the external clock signal input to the semiconductor chip by one cycle. Various timing network embodiments are described and claimed.

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