Clock run controller

Details Clock run controller Clock run controller

1998-09-30

2001-05-29

Wiley, David A. (Department: 2155)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C710S120000

Reexamination Certificate

active

06240522

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
This application related to computer system power management, and more particularly to power management in portable computer systems.
Background: PCI Bus
PCI, or Peripheral Component Interconnect, is a standard for interconnecting the peripherals, e.g. cards which are plugged into the motherboard) with both the system memory and the CPU of a computer system. Full technical details may be found in the
PCI Local Bus Specification
2.1 (PCI SIG, 1995), which is hereby incorporated by reference. It was designed from the start to alleviate many of the headaches that installation of a new card into an ISA bus-based computer would cause (IRQ conflicts, address conflicts, etc.). All PCI standards are set by a committee to ensure wide industry support. The PCI Bus is described in detail below.
Background: PCI Bridge
Overview and Terminology
A PCI to PCI (P2P) bridge provides a connection path between two independent PCI busses. The primary function of the bridge is to increase “load out” on the PCI bus. Because the PCI bus driver is limited as to how many devices it can drive on a single bus, a P2P bridge is used to allow more loads (devices) to be used on the system. The P2P birdge then manages transactions between a master on one PCI bus and a target on the other PCI bus. PCI to PCI bridges provide system and option card designers the ability to overcome electrical loading limits by creating hierarchical PCI busses. To aid in the discussion of PCI to PCI bridge architecture the following terminology is used:
initiating bus—the master of a transaction that crosses a PCI to PCI bridge is said to reside on the initiating bus.
target bus—the target of a transaction that crosses a PCI to PCI bridge is said to reside on the target bus.
primary interface—the PCI interface of the PCI to PCI bridge that is connected to the PCI bus nearest to the CPU is referred to as the primary PCI interface.
secondary interface—the PCI interface of the PCI to PCI bridge that is connected to the PCI bus farthest from the CPU is referred to as the secondary PCI interface.
downstream—transactions that are forwarded from the primary interface to secondary interface of a PCI to PCI bridge are said to be flowing downstream.
upstream—transactions that are forwarded from the secondary interface to primary interface of a PCI to PCI bridge are said to be flowing upstream.
Thus, a PCI to PCI bridge has two PCI interfaces, the primary and secondary. Each interface is capable of either master or target operation. The bridge functions as a target on the initiating bus on behalf of the target that actually resides on the target bus. Likewise, the bridge functions as a master on the target bus on behalf of the master that actually resides on the initiating bus.
FIG. 4
illustrates two typical applications for a PCI to PCI bridge. A PCI to PCI bridge allows transactions between a master on one PCI interface to a target on the other interface as illustrated in FIG.
5
.
Background: PCI Clock Run
The PCI clock run protocol defines a standard for dynamically reducing the PCI clock to reduce power consumption. In the PCI Specification, it is stated that all components (with a few exceptions) must work with frequencies up to 33 Mhz. When the system stops the clock it must be stopped in the low state and the clock line must remain low until the clock is restarted.
FIG. 6
shows the conventional agent roles in the clocking architecture. In this figure, the central resource (clock controller logic) controls modulation of the PCI clock and monitors and drives the CLKRUN# (more fully described below) to implement the clocking protocol. The master is any PCI master device which comprehends the clock control protocol and uses the CLKRUN# line to request a clock running state in order to assert REQ# and receive ownership of the bus. The target is any PCI target device which may require PCI clocks beyond the 4 clocks guaranteed at the end of a transfer cycle. It uses the CLKRUN# line to request that the clock remain running for a period of time.
Background: PCI CLKRUN# Signal
The CLKRUN# signal is optional and is defined for portable (mobile) computer systems. The PCI specification states that the clock may be stopped or its frequency changed, it does not define a method for determining when to stop or slow down the clock. The PCI specification also fails to define a method for determining when to restart the clock.
Conventional portable systems include a central resource that includes the PCI clock generation logic. CLKRUN# is a sustained tri-state input/output signal which the clock controlling logic keeps asserted when the clock is running normally. When the clock has been stopped or slowed, the clock controlling logic monitors CLKRUN# to recognize requests from devices for a change to be made in the state of the PCI clock signal. The clock cannot be stopped if the bus is not idle.
Before stopping or slowing down the clock frequency, the clock control logic deasserts CLKRUN# for one clock to signal an impending change in the clock state. CLKRUN# is first driven high (deasserted) for one clock, then the clock control logic tri-states the CLKRUN# output driver. The keeper resistor on CLKRUN# then maintains the deasserted state of CLKRUN# during the time the clock is stopped or slowed.
The clock will continue to run unchanged for a minimum of four clocks after the de-assertion of CLKRUN#. After CLKRUN# deassertion, the clock control logic must monitor CLKRUN# for two possible cases:
1. When the clock generation logic has deasserted CLKRUN#, indicating its intention to stop (or slow) the clock, the clock must continue to run for a minimum of four clocks. During this period of time, a device which requires continued clock operation may reassert CLKRUN# for two PCI clock cycles to request continued generation of CLK. When the clock control logic senses that CLKRUN# is reasserted, it reasserts CLKRUN# and continues to generate the clock, instead of slowing or stopping it. The PCI Specification does not define the period of time that the clock should continue to run after a request for continued operation.
2. After the clock has been stopped or slowed, a target may require clock restart in order to request use of the bus. Prior to bus activity, the target must first request clock restart. This is accomplished by assertion of CLKRUN#. When the clock control logic detects the assertion of CLKRUN# by another device, it turns on (or speeds up) the clock and turns on its CLKRUN# output driver to assert CLKRUN#. When the target device detects that CLKRUN# has been asserted for two rising-edges of the PCI CLK signal, the master may then tri-state its CLKRUN# output driver.
Background: PCI Bridge Clock Run
PCI Clock Run is described in the PCI Mobile Design Guide.
FIG. 7
shows a typical bridge CLKRUN# routing, in which PCR# is the primary bus CLKRUN#, SCR# is the secondary bus CLKRUN#, PEN is the primary bus enable for the CLKRUN# driver, and SEN is the secondary bus enable for the CLKRUN# driver.
When using the clock run protocol in an architecture with multiple busses and bridges, the routing of the clock and the relationship of the frequencies between the multiple busses must be considered. In general, the bridge itself contains the clocking resources for the secondary bus, but not the primary bus. The bridge does not drive CLKRUN# high on the primary bus, i.e. it does not act as a central resource for the primary bus. The bridge does drive CLKRUN# high on the secondary bus to indicate request to stop/slow the clock.
Note that a PCI device implementing clock run has an additional requirement when considering when to restart the clock. The bridge still has the first two defined above: clock run protocol and a clock restart. In addition to these, the bridge now must recognize when a superior bus transaction is being targeted to a device on the bridge's bus. When t

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