Clock regeneration circuit

Details Clock regeneration circuit Clock regeneration circuit

2007-10-26

2010-11-16

Elamin, Abdelmoniem (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S001000, C375S354000, C375S356000, C358S001900

Reexamination Certificate

active

07836323

ABSTRACT:
There is disclosed a clock regeneration circuit having a PCR buffer including a register which buffers a PCR extracted from a transmission signal, a counter which counts a reception side reference clock CKr, an STC buffer including a register which buffers a counted value of the counter, and a CPU which generates a signal indicating a difference between a transmission side reference clock and the reception side reference clock CKr based on values held in the PCR buffer and the STC buffer. If, at this point, a new PCR is input before the values held in the PCR buffer and the STC buffer are read by the CPU, the PCR buffer and the STC buffer are not updated.

REFERENCES:
patent: 6441847 (2002-08-01), Link et al.
patent: 6718476 (2004-04-01), Shima
patent: 7483173 (2009-01-01), Sadowara
patent: 7542371 (2009-06-01), Huang
patent: 2005/0226359 (2005-10-01), Uehara
patent: 2006/0203266 (2006-09-01), Sadowara
patent: 2007/0047374 (2007-03-01), Huang
patent: 11-225136 (1999-08-01), None

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