Clock rate compensation for a low frequency slave device

Details Clock rate compensation for a low frequency slave device Clock rate compensation for a low frequency slave device

1996-09-26

1999-07-20

Butler, Dennis M.

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

713503, G06F 104

Patent

active

059251352

ABSTRACT:
A slave device having clock rate compensation circuitry for low frequency operation. The slave device is coupled to a bus having a first operating frequency yet uses a slave clock signal having a frequency less than the first operating frequency. The slave device includes a bus clock driver circuit coupled to a bus clock interface for a bus clock signal. A slave controller state machine is clocked by the slave clock signal and accordingly operates at less than the first operating frequency. The clock rate compensation circuitry receives the bus clock signal, a data signal, and the slave clock signal, and synchronizes bus events for the state machine. The clock rate compensation circuitry also asynchronously begins a bus clock signal stretching period.

REFERENCES:
patent: 5371880 (1994-12-01), Bhattacharya
patent: 5696994 (1997-12-01), Pang
Programmable Logic Devices, Data Handbook, Phillips Semiconductors, (1993), pp. 689-709.

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