Clock power reduction technique using multi-level voltage...

Details Clock power reduction technique using multi-level voltage... Clock power reduction technique using multi-level voltage...

2002-05-28

2003-11-11

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S095000, C326S098000, C326S081000, C326S083000, C326S017000, C326S121000, C326S119000

Reexamination Certificate

active

06646472

ABSTRACT:

BACKGROUND OF INVENTION
Modern high performance microprocessors have an ever-increasing number of circuit elements and an ever-rising clock frequency. Also, as the number of circuits that can be used in a central processing unit (CPU) has increased, the number of parallel operations has risen. As CPU performance continues to increase, the result has been a larger number of circuits switching at faster rates.
Higher frequencies and data throughput cause a processor to consume increased power. The power dissipated by a circuit is a quadratic function of the supply voltage. Reducing the supply voltage may decrease the power dissipated by a circuit; however, reducing the supply voltage also increases the delay of the circuit. Slowing the speed of the circuit may cause some CPU activities to be incomplete at the end of a cycle. The effect may lead to loss of data in a CPU or incorrect results. Thus, from a design perspective, power is an important consideration. Power is a consideration in the design of a broad range of integrated circuits, including CPUs.
As shown in
FIG. 1
, a typical computer system (
10
) has, among other components, a microprocessor (
12
), one or more forms of memory (
14
), integrated circuits (
16
) having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths (
19
), e.g., wires, buses, etc., to accomplish the various tasks of the computer system (
10
).
In order to properly accomplish such tasks, the computer system (
10
) relies on the basis of time to coordinate its various operations. To that end, a crystal oscillator (
18
) generates a system clock signal (referred to and known in the art as “reference clock signal” and shown in
FIG. 1
as SYS_CLK) to various parts of the computer system (
10
). Modern microprocessors and other integrated circuits, however, are typically capable of operating at frequencies significantly higher than the system clock signal, and thus, it becomes important to ensure that operations involving the microprocessor (
12
) and the other components of the computer system (
10
) use a proper and accurate reference of time.
One component used within the computer system (
10
) to ensure a proper reference of time among a system clock signal and a microprocessor clock signal, i.e., “chip clock signal,” is a type of clock generator known as a phase locked loop, or “PLL” (
20
). The PLL (
20
) is an electronic circuit that controls an oscillator such that the oscillator maintains a constant phase relative to a system clock signal. Referring to
FIG. 1
, the PLL (
20
) has as its input the system clock signal, which is its reference clock signal, and outputs a chip clock signal (shown in
FIG. 1
as CHIP_CLK) to the microprocessor (
12
). The system clock signal and chip clock signal have a specific phase and frequency relationship controlled by the PLL (
20
). This relationship between the phases and frequencies of the system clock signal and chip clock signal ensures that the various components within the microprocessor (
12
) use a controlled and accounted for reference of time.
A significant portion of the power consumed by a CPU occurs from the activities of generating and propagating the chip clock signal to various circuits on the CPU. When a CPU pipeline stalls, the chip clock signal continues to consume power regardless of the lack of processing. For example, a memory miss on the on-chip cache creates a situation in which the CPU may stall while the required information is fetched from off-chip memory or storage. During the stall, the chip clock signal continues to run even though no processing is performed with the circuits that are stalled. The chip clock signal operation is a significant portion of the power consumed during a pipeline stall.
FIG. 2
shows a representative PLL (
200
). The PLL (
200
) includes a PLL core (
202
) and a clock signal distribution network (
220
). The PLL core (
202
) generates the CHIP_CLK (
203
) signal based on a SYS_CLK (
201
) signal, any multiplication factor programmed in the PLL core (
202
), and a feedback loop signal (
211
).
The clock signal distribution network (
220
) includes multiple inverters (
204
). The clock signal distribution network (
220
) supplies a copy of the CHIP_CLK (
203
) signal to a variety of different circuits (not shown) on an integrated circuit. The different circuits may receive a copy of the CHIP_CLK (
203
) signal from signals (
205
,
207
,
209
) and from feedback loop signal (
211
) in the clock signal distribution network (
220
). The multiple inverters (
204
) may be located at physically distant locations from each other. The multiple inverters (
204
) buffer the CHIP_CLK (
203
) signal so that transition edges of each copy of the CHIP_CLK (
203
) signal at each signal (
205
,
207
,
209
) and feedback loop signal (
211
) occurs within a specified time duration. The multiple inverters (
204
) allow the capacitive load created by the variety of different circuits (not shown) connected to the signals (
205
,
207
,
209
) and feedback loop signal (
211
) to be properly driven.
The feedback loop signal (
211
) provides a mechanism for the PLL core (
202
) to adjust for any errors in the PLL output, CHIP_CLK (
203
) signal. The feedback loop signal (
211
) is a delayed copy of the CHIP_CLK (
203
) signal. The feedback loop signal (
211
) provides a clock signal that must stay in synchronization with the system clock signal, SYS_CLK (
201
).
The PLL core (
202
) aligns the transition edge and frequency of the SYS_CLK (
201
) signal and the feedback loop signal (
211
). The PLL core (
202
) adjusts its output frequency in order to zero any phase and frequency difference between the SYS_CLK (
201
) signal and the feedback loop signal (
211
). The PLL core (
202
) may include a multiply-by-N block to generate the CHIP_CLK (
203
) signal at N times the frequency of the SYS_CLK (
201
) signal. Multiplying the SYS_CLK (
201
) signal is useful when the CHIP_CLK (
203
) signal must have a higher frequency than the SYS_CLK (
201
) signal. By adding a divide by N block to the feedback loop signal (
211
) input to the PLL core (
202
), the feedback clock signal (
211
) frequency should be divided by N times to allow the phase and frequency difference between the SYS_CLK (
201
) signal and the feedback loop signal (
211
) to zero.
Higher frequencies and data throughput cause a processor to consume increased power. The power dissipated by a circuit is a quadratic function of the supply voltage. In particular, power is equal to the capacitance of the load multiplied by the frequency of switching multiplied by the square of the supply voltage. That is, P=C
LOAD
fV
DD
2
, where P is power, C
LOAD
is the capacitance of the load, f is frequency, and V
DD
is the supply voltage. Reducing the supply voltage may reduce the power dissipated; however, reducing the supply voltage also increases the delay of a circuit. For example, power consumed by the inverters (
204
) may be reduced by reducing the supply voltage. Reducing the supply voltage may decrease the power dissipated by the inverters (
204
); however, reducing the supply voltage also increases the delay of the inverters (
204
). Slowing the speed of the circuit may cause some CPU activities to be incomplete at the end of a cycle.
In
FIG. 2
, the clock distribution network (
220
) may be connected to a voltage regulator circuit. The voltage regulator circuit provides a means to reduce the supply voltage. Reducing the supply voltage of a voltage regulator circuit, however, may take hundreds, if not thousands, of clock cycles to adjust to a new supply voltage.
SUMMARY OF INVENTION
According to one aspect of the present invention, an integrated circuit comprises a first power supply path leading to a first voltage; a second power supply path leading to a second voltage; a power reduction signal to enable a reduction in power on the integrated circuit; and a clock driver circu

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