Clock path control circuit and semiconductor memory device...

Details Clock path control circuit and semiconductor memory device... Clock path control circuit and semiconductor memory device...

2011-03-22

2011-03-22

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S194000, C365S191000, C365S233100, C365S233110

Reexamination Certificate

active

07911853

ABSTRACT:
A clock path control circuit includes a clock control signal generating unit configured to generate a clock control signal having an activation period corresponding to an activation period of a data input buffer; and a clock transfer unit configured to provide a clock signal to a write clock path in response to the clock control signal during the activation period of the clock control signal.

REFERENCES:
patent: 7715252 (2010-05-01), Lee
patent: 2007/0257717 (2007-11-01), Yoon
patent: 2008/0137472 (2008-06-01), Schnell et al.
patent: 100632626 (2006-09-01), None
Notice of Preliminary Rejection issued from Korean Intellectual Property Office on Mar. 31, 2010.

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