Clock noise filter for integrated circuits

Details Clock noise filter for integrated circuits Clock noise filter for integrated circuits

1994-12-30

1996-07-23

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Metastable state prevention

326 22, 327291, H03K 1900

Patent

active

055393373

ABSTRACT:
A method and apparatus for providing a clock noise filter are described. The clock noise filter uses a transparent latch which has a trigger input and a data input. The data input is coupled to receive an input clock signal to be filtered. The output of the latch is the filtered clock signal. The filtered clock signal has a logic state which corresponds to the logic state of the input clock signal when the trigger input has a first predetermined logic state, and the filtered clock signal is inhibited from changing logic state when the trigger input has a second predetermined logic state. A trigger circuit is provided which has an input coupled to the output of the latch and an output coupled to the trigger input of the latch. The trigger circuit outputs the second predetermined logic state to the trigger input of the latch for a time interval in response to a change in logic state of the filtered clock signal and outputs the first predetermined logic state after the time interval has expired. The trigger circuit uses a delay stage to provide a delayed filtered clock signal to a logic gate. The logic gate receives the filtered clock signal and the delayed filtered clock signal and outputs the first and second predetermined logic states to the trigger input of the latch, depending upon the relative logic states of the filtered clock signal and the delayed filtered clock signal.

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