Clock distribution system

Details Clock distribution system Clock distribution system

2007-10-30

2007-10-30

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C716S030000

Reexamination Certificate

active

10468168

ABSTRACT:
A clock distribution system for an integrated circuit comprising a plurality of regions (1, 2, 3) connected by a communications bus (12). Each region comprises a functional block (10a,10b,10c) and at least one bus node (14a,14b,14c) for connecting a respective functional block to the communications bus (12). A distributed clock signal (16) is allowed to skew between regions, but synchronised within respective regions. A predetermined clock insertion delay (20a,20b,20c,22a,22b,22c) is inserted in each functional block and bus node.

REFERENCES:
patent: 5122679 (1992-06-01), Ishii et al.
patent: 5398262 (1995-03-01), Ahuja
patent: 5822779 (1998-10-01), Intrater et al.
patent: 5828870 (1998-10-01), Gunadisastra
patent: 5969559 (1999-10-01), Schwartz
patent: 6218861 (2001-04-01), Sudo et al.
patent: 6240524 (2001-05-01), Suzuki
patent: 6305001 (2001-10-01), Graef
patent: 0 903 660 (1999-03-01), None

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