Clock distribution circuit, semiconductor integrated circuit...

Details Clock distribution circuit, semiconductor integrated circuit... Clock distribution circuit, semiconductor integrated circuit...

2007-06-11

2010-10-05

Elamin, Abdelmoniem (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S401000, C713S002000, C713S002000, C331S017000, C331S025000, C327S156000, C327S157000

Reexamination Certificate

active

07809971

ABSTRACT:
A clock distribution circuit, which is provided in IC that has a first sequential circuit receiving first clock through a first branch node on a first clock network, a second sequential circuit receiving second clock through a second branch node on a second clock network, and a data transfer path between the first and second sequential circuits, includes: a first PLL receiving a first feedback clock that is the first clock branched at the first branch node and outputting the first clock to the first clock network based on the first feedback clock; and a second PLL receiving a second feedback clock that is the second clock branched at the second branch node and outputting the second clock to the second clock network based on the second feedback clock. A branch node is provided at least one of between the first PLL and the first branch node and between the second PLL and the second branch node.

REFERENCES:
patent: 6201448 (2001-03-01), Tam et al.
patent: 6211740 (2001-04-01), Dai et al.
patent: 6624681 (2003-09-01), Loyer et al.
patent: 7005907 (2006-02-01), Ibuka
patent: 2002/0140487 (2002-10-01), Fayneh et al.
patent: 2004-15032 (2004-01-01), None
patent: 2004-241699 (2004-08-01), None

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