Clock control hierarchy for integrated microprocessors and...

Details Clock control hierarchy for integrated microprocessors and... Clock control hierarchy for integrated microprocessors and...

2005-10-04

2009-12-01

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S324000, C713S500000, C714S030000, C714S034000

Reexamination Certificate

active

07627771

ABSTRACT:
A clock control hierarchy is provided that is comprised of synchronous and asynchronous hold request signals that are used to start and stop functional units of a chip. Pervasive logic is provided that uses a synchronous “chip hold” signal and asynchronous latch/functional unit hold signals to individually target functional units and latches that are to remain in a held state once the “chip hold” state is released. With the present invention, a chip hold request is first activated followed by scannable latch and non-scannable latch hold requests being activated to identify which latches will be clocked or not clocked when the chip hold is released. Functional unit hold signals are activated to place certain ones of the functional units of the chip in a hold state. The chip hold request is deactivated and the chip operates with the selected functional units and latches being maintained in a held state.

REFERENCES:
patent: 5774701 (1998-06-01), Matsui et al.
patent: 5928359 (1999-07-01), Lee
patent: 6173386 (2001-01-01), Key et al.
patent: 6662313 (2003-12-01), Swanson et al.
patent: 6792527 (2004-09-01), Allegrucci
patent: 6950963 (2005-09-01), Parson et al.
patent: 7055117 (2006-05-01), Yee
patent: 7219265 (2007-05-01), Yee
patent: 7325164 (2008-01-01), Swanson et al.
patent: 2003/0100133 (2003-05-01), Eidson et al.
patent: 2004/0153838 (2004-08-01), Swanson et al.
patent: 2005/0076278 (2005-04-01), Vermeulen et al.
patent: 2005/0149892 (2005-07-01), Yee
patent: 2005/0193254 (2005-09-01), Yee

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