Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2006-03-28
2008-05-27
Weiss, Howard (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S407000, C438S458000, C438S620000, C257S607000, C257S620000
Reexamination Certificate
active
07378330
ABSTRACT:
A method of forming substrates, e.g., silicon on insulator, silicon on silicon. The method includes providing a donor substrate, e.g., silicon wafer. The method also includes forming a cleave layer on the donor substrate that contains the cleave plane, the plane of eventual separation. In a specific embodiment, the cleave layer comprising silicon germanium. The method also includes forming a device layer (e.g., epitaxial silicon) on the cleave layer. The method also includes introducing particles into the cleave layer to add stress in the cleave layer. The particles within the cleave layer are then redistributed to form a high concentration region of the particles in the vicinity of the cleave plane, where the redistribution of the particles is carried out in a manner substantially free from microbubble or microcavity formation of the particles in the cleave plane. That is, the particles are generally at a low dose, which is defined herein as a lack of microbubble or microcavity formation in the cleave plane. The method also includes providing selected energy to the donor substrate to cleave the device layer from the cleave layer at the cleave plane, whereupon the selected energy is applied to create a controlled cleaving action to remove the device layer from a portion of the cleave layer in a controlled manner.
REFERENCES:
patent: 5827751 (1998-10-01), Nuyen
patent: 5877070 (1999-03-01), Goesele et al.
patent: 5961877 (1999-10-01), Robinson et al.
Bryan Michael A.
En William G.
Henley Francois J.
Rao Steven H
Silicon Genesis Corporation
Weiss Howard
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