Circuits, systems and methods for modifying data stored in a mem

Details Circuits, systems and methods for modifying data stored in a mem Circuits, systems and methods for modifying data stored in a mem

1995-04-19

1998-03-24

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36523006, G11C 800

Patent

active

057320241

ABSTRACT:
A memory system 104 is provided which includes an array 200 of memory cells arranged in rows and columns. Circuitry 207, 208, 209, 210 is also provided for selectively performing logic operations on a bit of data stored in a selected memory cell using a bit of received modifying data. Circuitry 207, 208, 209, 210 for performing logic operations is operable during an AND operation to write the bit of modifying data into the selected memory cell when the bit of modifying data is a logic zero and maintains an existing bit stored in the selected cell when the bit of modifying data is a logic one.

REFERENCES:
patent: 5195056 (1993-03-01), Pinkham
patent: 5432743 (1995-07-01), Kusakari
patent: 5544115 (1996-08-01), Ikeda
"Patent Abstracts of Japan" vol. 18, No. 264, p. 174 on May 19, 1994 Abstract JPA06036555.
"Patent Abstracts of Japan" vol. 18, No. 333, p. 1759 on Jun. 23, 1994 Abstract No. JPA06076565.

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