Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1994-09-30
1996-03-19
Zarabian, A.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365205, 3652385, G11C 1140
Patent
active
055008194
ABSTRACT:
A memory 200 is provided which includes an array 201 of volatile memory cells 202. Addressing circuitry 205, 213 is included for providing access to selected ones of the memory cells 202. Master read/write circuitry 208 is included for reading and writing data into the selected memory cells 202. First slave circuitry 210, 211 is provided for storing data for exchange with the master read/write circuitry 208. Second slave circuitry 210/211 is also provided for storing data for exchange with the master read/write circuitry 208. Control circuitry 206, 214, 215 controls the exchanges of data between the master read/write circuitry 208 and the first and second slave circuitry 210, 211.
REFERENCES:
patent: 5088062 (1992-02-01), Shikata
patent: 5278790 (1994-01-01), Kanabara
patent: 5305284 (1994-04-01), Iwase
Cirrus Logic Inc.
Zarabian A.
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