Circuits for driving FRAM

Details Circuits for driving FRAM Circuits for driving FRAM

2007-12-04

2007-12-04

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S194000, C365S230080, C365S233500

Reexamination Certificate

active

11301920

ABSTRACT:
A drive circuit of a FRAM (Ferroelectric Random Access Memory) includes an address buffer circuit that buffers an applied external address signal and generates an internal address signal, and detects a transition of the internal address signal and generates address transition detection signals for respective internal address signals. The FRAM includes a composite pulse signal generating circuit which limits a subsequent generation of a composite pulse signal for a delay interval provided after a generation of a previous composite pulse signal, in generating the second composite pulse signal obtained by totaling the respective address transition detection signals. The FRAM includes an internal chip enable buffer circuit which generates an internal chip enable signal to generate an internal control signal, in response to the composite pulse signal.

REFERENCES:
patent: 6590829 (2003-07-01), Takeuchi
patent: 6889268 (2005-05-01), Chae et al.
patent: 6967890 (2005-11-01), Shen

Affiliated with

Also associated with

Rating

Circuits for driving FRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuits for driving FRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuits for driving FRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3877416