Circuits and methods using vertical complementary transistors

Details Circuits and methods using vertical complementary transistors Circuits and methods using vertical complementary transistors

2000-02-29

2001-09-25

Dang, Trug (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S268000, C438S270000, C438S272000, C438S589000

Reexamination Certificate

active

06294418

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to circuits and methods using vertical, complementary transistors.
BACKGROUND OF THE INVENTION
Integrated circuit technology relies on transistors to formulate vast arrays of functional circuits. The complexity of these circuits requires the use of an ever increasing number of linked transistors. As the number of transistors required increases, the surface area that can be dedicated to a single transistor dwindles. It is desirable then, to construct transistors which occupy less surface area on the silicon chip/die.
Integrated circuit technology uses transistors conjunctively with Boolean algebra to create a myriad of functional digital circuits, also referred to as logic circuits. In a typical arrangement, transistors are combined to switch or alternate an output voltage between just two significant voltage levels, labeled logic 0 and logic 1. Most logic systems use positive logic, in which logic 0 is represented by zero volts, or a low voltage, e.g., below 0.5 V; and logic 1 is represented by a higher voltage.
One method in which these results are achieved involves Complementary Metal-Oxide Semiconductor (CMOS) technology. CMOS technology comprises a combination of oppositely doped Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs) to achieve the switching mechanism between voltage levels associated with logic 0 and that of logic 1. This configuration is likewise referred to as an inverter. Conventional CMOS inverters consume an appreciable amount of chip surface area, even despite ongoing reductions in the critical dimensions that are achievable with conventional photolithography techniques. The critical dimension (F) represents the minimum lithographic feature size that is imposed by lithographic processes used during fabrication.
Some companies have dabbled with use of vertical transistors, but have limited the use to circuits such as memories. The use of vertical transistors in memories generally focuses on the placement, arrangement and size of the charge storage node. The charge storage node is conventionally a capacitor of one form or another. Capacitors have individual space requirements and obstacles which have to be overcome in order to retain data stored under low power supplies. Logic circuit transistors similarly have individual space requirements and obstacles which have not been addressed.
Accordingly, what is needed is improved configuration for transistors, suitable for use in logic circuits, which will conserve surface space on the semiconductor die.
SUMMARY OF THE INVENTION
In one embodiment, an inverter is provided. The inverter comprises a first vertically configured transistor extending outwardly from a semiconductor substrate and a second vertically configured transistor similarly extending outward from the semiconductor substrate. There is provided electrical contact between source/drain regions of the first and second vertically configured transistors to provide an output for the inverter, and a gate contact is included. The gate contact interconnects the vertically configured transistors wherein the gate contact comprises an input to the inverter.
The vertically configured transistors each have a number of sides, first and second source/drain regions, a body region and a gate. The first and second transistors are contained in separate pillars of single crystalline semiconductor material. The gate contact interconnects the gates of the first and second transistors. In the inverter the body region and first and second source/drain regions of the second transistors are oppositely doped from the corresponding body region and first and second source/drain regions of the first transistor.
In another embodiment, an inverter array is provided. The array comprises multiple complementary pairs of transistors extending outwardly from a semiconductor substrate. The multiple complementary pairs have upper surfaces and each transistor in a pair has a vertically stacked body region, and first and second source/drain region and a gate. There is provided an electrical contact between the source/drain regions of the transistors in each complementary pair. This electrical contact is found between the second source/drain regions of the transistors in each complementary pair and further includes an output to other ones of the multiple complementary pairs of transistors. A plurality of isolation trenches extend parallel to and separate the multiple complementary pairs of transistors. A gate contact is provided for each complementary pair of transistors. The gate contact communicates with the body region of each transistor in the complementary pair and further includes an electrical input adapted to receive electrical signals from both external sources as well as other ones of the multiple complementary pairs of transistors. The gate contact is located below the upper surface of the multiple complementary pairs of transistors.
Another embodiment includes an integrated logic circuit. The logic circuit has multiple complementary pairs of transistors extending outwardly from the substrate having an upper surface. Each transistor in the complementary pairs includes a vertically stacked body region between first and second source/drain regions. A gate contact is shared between each complementary pair of transistors. This gate contact couples to the body region of each transistor in the pair. As above in the array, the gate contact is below the upper surface of the multiple complementary pairs of transistors. The gate contact also includes an input. An electrical contact couples each transistor in the complementary pair of transistors such that each complementary pair of transistors forms an inverter. An output for the inverter is connected to the electrical contact. A metallization layer selectively interconnects the inputs and outputs of the inverters to form a logic circuit that accepts inputs and produces one or more logical outputs.
In another embodiment, an input/output device is provided. The input/output device comprises a functional circuit having a plurality of components. A logic device couples to the functional circuit. This logic device has at least one inverter. The inverter included in the logic device further comprises a complementary pair of transistors extending outwardly from a semiconducting substrate. Each complementary pair has an upper surface. Each transistor in the complementary pair has a body region vertically stacked between first and second source/drain regions and has a gate region. There is a gate contact which couples the gates in each complementary pair of transistors. The gate contact is below the upper surface of the multiple complementary pairs of transistors and the gate contact has an input for each inverter. There is an electrical contact between the second source/drain region in each complementary pair of transistors. This electrical contact has an output for the inverter. A metallization layer is included that selectively interconnects the inputs and outputs of selected inverters in the array to implement the logical function and form the functional circuit.
In another embodiment, a method of fabricating an inverter device is provided. The method includes forming a first transistor in a first pillar of single crystalline semiconductor material that extends outwardly from a substrate and forming a second transistor in a second pillar of single crystalline semiconductor material that extends outwardly from the substrate. Both the first and second pillar are formed with a number of sides. The method includes forming the first and second transistor to include a body region as well as first and second source/drain regions that are vertically aligned. The method includes forming the first and second transistors to include a region associated with a side of the transistors. A gate contact is formed so as to communicate with the gate regions of both first and second transistors. A metal contact is formed

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