Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction
Reexamination Certificate
2006-06-20
2006-06-20
Lamarre, Guy (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Skew detection correction
Reexamination Certificate
active
07065684
ABSTRACT:
Described are methods and circuits for precisely measuring signal propagation delays between synchronous memory elements. The memory elements are configured as a down counter that produces a test signal with a test period that is some multiple of a clock common to the memory elements. When the signal path is sufficiently fast for data to transfer between the synchronous memory elements in a single clock cycle, the test period is one multiple of the clock period. However, when the signal path fails to pass either rising or falling edges between the synchronous memory elements in a single clock cycle, the test period is increased by one clock period, and when the signal path fails to pass both rising and falling edges in a single clock cycle, the test period is increased by two clock periods.
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Behiel Arthur Joseph
Kerveros James C.
Lamarre Guy
Maunu LeRoy D.
Xilinx , Inc.
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