Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-12-20
2003-05-20
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S014000
Reexamination Certificate
active
06567971
ABSTRACT:
The present invention relates, in general, to integrated circuits and, more specifically, to methods of and program product for designing integrated circuits.
BACKGROUND OF THE INVENTION
A typical logic circuit design process includes the steps of writing a description of the desired circuit in a high-level hardware description language (HDL), synthesizing the circuit represented by the HDL using a library of pre-designed circuits (herein called “logic cells”) from a hardware fabrication technology, including for example, NAND gates and flip-flops, simulating the resulting synthesized circuit, analyzing the synthesized circuit for timing and other characteristics using circuit simulator software and/or a circuit timing analyzers; and, if the performance of the synthesized circuit is not acceptable, modifying the HDL description and repeating the above steps.
This design process has been used by thousands of designers, for thousands of designs. Logic circuit synthesis software optimizes combinatorial and sequential logic, minimizing area and power while meeting circuit propagation delay constraints. Yet, there are functions with additional constraints, which are not presently handled by commercially available synthesis software. For example, using only an HDL description, synthesis software cannot build a logic circuit whose signal propagation delay can be adjusted in increments of less than the delay of a logic gate. Such a logic circuit is a useful building block for ring oscillators, clocks, distribution circuits, and timing measurement circuits, for example.
One way of building functions not handled by synthesis software is to have the manufacturer of the logic cells create a new logic cell to implement the function. However, this method is costly, time consuming, and not easily portable between hardware fabrication technologies.
Another approach is to write “structural HDL”, a style of HDL in which the detailed logic structure of the desired function is specified in terms of sub-functions that are predictably synthesized from logic cells. These sub-functions are then tagged to indicate that the synthesis software should not attempt to optimize or change these sub-functions (for example, one commercial tool uses the key word “don't
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touch”). This approach will work if the writer of the structural HDL knows some essential performance parameters of the sub-functions, such as signal propagation delays and output drive strength (or “drive factor”). If the designer knows which logic cells the synthesis software will use when constructing the sub-functions, he can inquire about the parameters of the pre-defined circuits. Delays, drive factors and other parameters for the pre-defined circuits are contained in synthesis and simulation models. Unfortunately, this data is generally encrypted and not available to the designer. Some modeling information for the logic cells is contained in documentation or data sheets produced by the manufacturer. However, this data is often incomplete or out of date. In spite of these obstacles, model delays and drive factors can be manually copied from data sheets and used to write structural HDL. The results typically vary due to errors in interpreting data sheets, out of date information, typographical errors, etc.
Another limitation resides in logic circuit simulator software (herein called “logic simulator”). Very small delay increments can be obtained by connecting a plurality of tristate gates in parallel and enabling all or a subset of the gates to switch in response to their data inputs. These circuits can be designed using the structural HDL plus the “don't-touch” method described earlier. However, logic simulators incorrectly simulate the delay as though only one tristate gate is switching. Transistor-level simulators will simulate the correct delay, but simulate very slowly for large circuits. Moreover, neither transistor models nor net lists of the pre-defined circuits are generally available to the logic designer.
SUMMARY OF THE INVENTION
The present invention seeks to provide a method for designing circuits to (a) allow the initial description of a circuit to be modified or adjusted to reflect hardware fabrication technology and (b) to allow modeling of circuits with software tools which are not otherwise capable of modeling the circuit.
The present invention is generally defined as a method of synthesizing a circuit, comprising synthesizing a high-level circuit description of a first circuit according to synthesis constraints and a circuit implementation technology to produce a synthesized first circuit; simulating the synthesized first circuit to derive values of performance parameters of the circuit implementation technology; modifying a high-level circuit description of a second circuit based on the derived values to produce a modified second circuit description; and synthesizing the modified second circuit description according to the synthesis constraints and a circuit implementation technology to produce a synthesized second circuit.
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Banzhaf Walter H.
Roy Aubin P. J.
Sunter Stephen K.
Dinh Paul
LogicVision, Inc.
Proulx Eugene E.
Smith Matthew
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