Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2001-02-13
2002-09-17
Cuneo, Kamand (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C361S777000, C361S768000, C361S783000, C257S778000
Reexamination Certificate
active
06452115
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-layer circuit board for mounting an electronic part such as a semiconductor chip or a semiconductor device having a number of electrodes, pads, or lands, hereinafter referred to as lands, arranged in a lattice form or in a staggered form.
2. Description of the Related Art
In modern semiconductor devices, the logic devices are becoming highly functional and highly integrated, feature more inputs and outputs, and are being mounted ever more densely. Therefore, products have been produced to compensate for a lack of space for forming lands, and to cope with increased numbers of inputs and outputs, by arranging lands like an array on the land-forming surface of a semiconductor chip.
FIG. 25
illustrates a prior art or mounting a semiconductor chip
4
on a substrate
5
relying on a flip chip connection. The semiconductor chip
4
shown here has lands
6
arranged on the outer peripheral edges thereof. Circuit patterns
7
are connected to the, lands
6
and are drawn outwardly. In this case the respective circuit patterns
7
are connected to the respective electrodes
6
on a single, common surface.
FIG. 24
illustrates the arrangement of lands on a wiring member for mounting a semiconductor chip having two rows of lands
6
arranged along the outer peripheral edges of the land-forming surface, and the arrangement of circuit patterns
7
connected to the lands
8
. In this example, the pattern
7
is drawn from an intermediate portion of the space between the adjacent two lands
8
; i.e., the respective circuit pattern
7
is drawn from the respective land
8
on a single common surface. In drawing the circuit patterns
7
from the lands
8
arranged in plural rows, it is general practice to connect a pattern on the land
8
of the inner side and to draw the pattern outwardly through the intermediate portion between the two adjacent lands
8
of the outer side.
When a number of lands are arranged like an array on the land-forming surface to increase the numbers of inputs and outputs, however, it becomes no longer possible to draw the wirings toward the outer side from all lands on the surface though it may vary depending upon the distance between the lands and the number of the lands.
To solve this problem, it has been contrived to form circuit boards in many layers for mounting a semiconductor chip, and to suitably arrange the circuit patterns on the laminated circuit boards, in order to electrically connect the lands to every land of the semiconductor chip and to make the circuit patterns.
FIG. 26
illustrates an example where a semiconductor chip
4
is mounted on a multi-layer circuit board obtained by laminating a plurality of layers. Thus, according to the method of laminating the plurality of layers, it becomes possible to electrically connect the semiconductor chip
4
having a number of lands
6
arranged like an array to the external connection terminals without causing the circuit patterns to interfere. In
FIG. 26
, reference numeral
7
a
denotes a circuit pattern of an inner layer, and
5
a
to
5
d
denote circuit boards which are the first to fourth layers.
When the semiconductor chip having lands arranged like an array is to be mounted on the circuit board, about two circuit boards may be laminated one upon the other provided the number of the lands is not very large. When the semiconductor chip has as many pins as, for example, 30×30 pins or 40×40 pins, however, the circuit boards must be laminated in 6 to 10 layers.
When the circuit boards in which the circuit patterns are very densely formed are to be laminated in many layers, there will be employed a high-density wiring method such as build-up method accompanied, however, by serious problems in regard to yield of the products, reliability and the cost of production. That is, when the circuit patterns are to be formed in many layers, vias are formed in each layer to accomplish an electric connection between the circuit patterns and the circuit patterns across the layer, and the layers are successively laminated, requiring a high degree of precision without, however, offering high degree of reliability. When many layers are laminated, furthermore, it is required that none of the layers is defective, involving further increased technical difficulty.
To produce a multi-layer circuit board by laminating circuit patterns in many layers, while maintaining a good yield, a reduction in the number of wiring layers could be an effective solution.
SUMMARY OF THE INVENTION
The present invention is concerned with a multi-layer circuit board for mounting an electronic part such as a semiconductor chip having as many as 40×40 pins arranged in an array on the side of the mounting surface or a semiconductor device having lands arranged in an array on the side of the mounting surface. The object of the present invention is to provide a multi-layer circuit board which makes it possible to mount an electronic part such as a semiconductor chip or a semiconductor device, despite a decreased number of circuit boards being laminated one upon the other, which features improved yield of production and which can be used as a highly reliable product. In order to accomplish the above-mentioned object, the present invention provides the following multi-layer circuit board.
The present invention provides a multi-layer circuit board formed by e.g., laminating a plurality of layers in order to mount an electronic part such as a semiconductor chip or a semiconductor device having many lands arranged in the form of an array. Upon contriving the arrangement of circuit patterns on each circuit layer, a multi-layer circuit board can be constituted by forming the circuit boards (wiring layers) in a decreased number of layers. There is no particular limitation on the method of fabricating the multi-layer circuit board, and various methods, such as a build-up method, can be employed.
Arrangements of lands of the electronic parts can be divided into a normal lattice arrangement and a staggered lattice arrangement. Here, when the lands are arranged in the normal lattice form or staggered lattice form, a problem arises in regard to how the circuit patterns can be arranged to accomplish the highest efficiency.
The circuit patterns pass through among the lands. In the practical products, therefore, the circuit patterns must be set depending upon the predetermined conditions such as pitch of lands, diameter of lands, width of patterns and gap between the patterns.
According to the present invention, the following method is employed for determining the arrangement of circuit patterns on each circuit board in a multi-layer circuit board formed by laminating the circuit boards. Upon arranging the circuit patterns according to this method, it is possible to form a multi-layer circuit board in the least number of layers.
First, considered below is a case where the lands are formed in a normal lattice arrangement maintaining an equal distance in the vertical and lateral directions.
Let it now be presumed that intermediate lands of a number of (n−2) do not exist except for the lands at both ends in the arrangement of lands of a number of n maintaining an equal distance, and that the number of wirings that can be passed (arranged) among the lands between both ends except the lands at both ends is m, then, m is given by the following formula,
m
=
{
(
land
pitch
)
×
(
n
-
1
)
-
(
land
diameter
)
-
(
space
between
patterns
)
}
+
(
pattern
width
+
space
between
patterns
)
where land pitch is a distance between the centers of the lands (“a” in FIG.
1
), land diameter is a diameter of the land (“b” in FIG.
1
), space between patterns is a minimum distance that must be maintained between the neighboring circuit patterns (“c” in FIG.
1
), and the pattern width is “d” in FIG.
1
.
If it is
Horiuchi Michio
Takubo Chiaki
Yoda Eiji
Cuneo Kamand
Pennie & Edmonds LLP
Shinko Electric Industries Co., Ltd
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