Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-27
2002-04-16
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S356000, C257S357000, C257S358000, C257S360000, C257S361000, C257S363000
Reexamination Certificate
active
06373104
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to circuits, and more particularly, to a circuit and method for reducing parasitic bipolar effects during electrostatic discharges.
BACKGROUND OF THE INVENTION
An integrated circuit or semiconductor device can be damaged when subjected to a voltage that is higher than the design voltage of the integrated circuit. Electrostatic discharge (“ESD”), originating from such sources as a mechanical chip carrier, a plastic chip storage device, or even a human being can generate a voltage that is many times greater than the design voltage of the integrated circuit. For example, the typical human body can supply an electrostatic discharge in excess of 4 kilovolts. For integrated circuits that operate at voltages of less than, for example, 5 volts, an electrostatic discharge of such proportions can be devastating.
In order to protect the internal circuitry from electrical overstress (EOS), or ESD, events, protection circuits are utilized, generally between the internal circuitry and the input/output (“I/O”) pins of the integrated circuit. One mechanism that can cause circuit failures during ESD events is a phenomenon known as “bipolar snapback”.
REFERENCES:
patent: 5019888 (1991-05-01), Scott et al.
patent: 5021853 (1991-06-01), Mistry
patent: 5157573 (1992-10-01), Lee et al.
patent: 5225702 (1993-07-01), Chatterjee
patent: 5440162 (1995-08-01), Worley et al.
patent: 5465189 (1995-11-01), Polgreen et al.
patent: 5903419 (1999-05-01), Smith
“Substrate Triggering and Salicide Effects on ESD Performance and Protection Circuit Design in Deep Submicron CMOS Processes,” Amerasekera, et al; IEEE; pp. 547-550 (1995).
“A Substrate Triggered Lateral Bipolar Circuit for High Voltage Tolerant ESD Protection Applications,” Smith.
“EOS/ESD Analysis of High-Density Logic Chips,” Ramaswamy, et al; EOS/ESD Symposium 96; pp. 6.4.1-6.4.6.
“Analysis of Snubber-Clamped Diode-String Mixed Voltage Interface ESD Protection Network for Advanced Microprocessors,” Voldman et al.; EOS/ESD Symposium 95; pp. 43-61.
Motorola Inc.
Wojciechowicz Edward
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