Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-04-12
2002-07-23
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S239000, C438S241000
Reexamination Certificate
active
06423602
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit manufacturing method and apparatus for activating an impurity ion-implanted into a silicon substrate through annealing, an anneal control method and apparatus for controlling the operation of the circuit manufacturing apparatus, and an information storage medium for storing a program as software which causes a computer for controlling the operation of the circuit manufacturing apparatus to perform various processing operations.
2. Description of the Related Art
In recent years, MOS transistors for use in logic circuits and the like have LDD (Lightly Doped Drain-Source) areas added on the inner sides of normal source/drain areas to suppress the occurrence of hot carriers and a reduction in breakdown voltage.
In current MOS transistors, however, the supply voltage decreases and the aforementioned purposes become less important. Thus, the concentration of the impurity in LDD areas is increased to achieve a lower resistance. This is called an extension area which is formed to have a concentration lower than that in normal source/drain areas and higher than that in conventional LDD areas.
Description is hereinafter made for a prior art of MOS transistor
10
of such structure with reference to FIG.
1
. In p-channel MOS transistor
10
illustrated herein as a prior art, gate insulating film
12
in predetermined pattern and p-type gate electrode
13
are stacked in turn on the surface of an n-type area of silicon substrate
11
, and side walls
14
are formed on both sides of gate insulating film
12
and gate electrode
13
.
A pair of p-type source/drain areas
15
is formed in surface portions of silicon substrate
11
on the outer sides of side walls
14
. A pair of p-type extension areas
16
is formed with channel area
17
interposed between them in surface portions of silicon substrate
11
on the inner sides of source/drain areas
15
.
Since MOS transistor
10
of the aforementioned structure has extension areas
16
located on the inner sides of source/drain areas
15
, it is possible to suppress the occurrence of hot carriers and a reduction in breakdown voltage similarly to a conventional LDD structure, and moreover, it shows a lower resistance than the conventional LDD structure.
In the aforementioned MOS transistor
10
, gate insulating film
12
is formed, for example, of a thermal oxidation film of silicon substrate
11
, and a p-type impurity such as boron is implanted into source/drain areas
15
, extension areas
16
, and gate electrode
13
for allowing them to serve as p-channels.
Now, a transistor manufacturing method of manufacturing MOS transistor
10
as described above is described in brief. The surface of silicon substrate
11
is first subjected to thermal treatment to form a thermal oxidation film on the entire surface, and gate electrode
13
is formed in a predetermined pattern on the surface of the thermal oxidation film.
Dry etching is performed with gate electrode
13
used as a mask to remove the portion of the thermal oxidation film which is not masked by gate electrode
13
from the surface of silicon substrate
11
. The thermal oxidation film remaining under gate electrode
13
thus constitutes gate insulating film
12
as shown in FIG.
2
A.
Next, as shown in
FIG. 2B
, a p-type impurity is lightly doped into the surface portions of silicon substrate
11
at the positions of extension areas
16
with gate electrode
13
used as a mask. Side walls
14
are formed on both sides of gate insulating film
12
and gate electrode
13
on the surface of silicon substrate
11
which includes the impurity ion-implanted thereinto, as shown in FIG.
2
C.
Then, as shown in
FIG. 2D
, a p-type impurity is deeply doped into the surface portions of silicon substrate
11
at the positions of source/drain areas
15
with side walls
14
used as masks, and the impurities thus ion-implanted into silicon substrate
11
are activated through annealing to form source/drain areas
15
and extension areas
16
, thereby completing p-channel MOS transistor
10
as shown in FIG.
1
.
For the annealing of silicon substrate
11
to form source/drain areas
15
and extension areas
16
as described above, an RTA (Rapid Thermal Anneal) method is typically used at present. As shown in
FIG. 3
, in the RTA method, silicon substrate
11
placed in an atmosphere of nitrogen or argon is raised in temperature to the annealing temperature of approximately 1000 (° C.) at the maximum rate of an anneal apparatus, and then decreased in temperature to normal temperature at the maximum speed.
In this manner, since the rise and decrease in temperature are performed at the maximum speed and the rise in temperature transitions directly to the decrease in temperature as spike anneal in the RTA method, unnecessary diffusion of an impurity can be prevented to form extension areas
16
in a proper concentration with small depths of junctions with silicon substrate
11
.
An alternative method of manufacturing MOS transistor
10
of the aforementioned structure is shown in
FIGS. 4A
to
4
F. Specifically, a p-type impurity is deeply doped into silicon substrate
11
at the positions of source/drain areas
15
with side walls
14
used as masks and then annealing is performed. After side walls
14
are removed, a p-type impurity is lightly doped into silicon substrate
11
at the positions of extension areas
16
with gate electrode
13
used as a mask. Side walls
14
are again formed and then annealing is again performed.
In this case, since the first annealing for activating source/drain areas
15
is not performed in the RTA method but as normal long-duration annealing, a defect due to the ion implantation is favorably recovered. In addition, since the second annealing for activating extension areas
16
is performed in the RTA method, extension areas
16
can be formed at low resistance with small depths of the junctions.
When the impurity for extension areas
16
is activated in silicon substrate
11
as described above, the annealing of silicon substrate
11
in the RTA method can result in extension areas
16
with a small depth of the junctions at low resistance. In the aforementioned annealing which involves the rise and decrease in temperature at the maximum rate, however, excessive stress applied to portions of silicon substrate
11
and the like may cause defects such as breakage or peeling in the portions.
To solve such a problem, temperature can be decreased at a lower speed as shown in FIG.
5
. However, as shown in
FIG. 6A
, a decrease in temperature of silicon substrate
11
which has been raised in temperature to the annealing temperature reduces the solid solubility of the ion-implanted impurity, and a decrease in temperature at a low speed causes high thermal energy to act on silicon substrate
11
and the impurity as shown in FIG.
6
B.
Accordingly, the decrease in temperature at a lower speed causes the impurity with a reduced solid solubility to be acted upon by thermal energy high enough to disconnect the impurity from silicon substrate
11
, which results in disconnection of the impurity from silicon substrate
11
. In this case, the impurity for extension areas
16
is unnecessarily diffused to increase depths of the junctions with silicon substrate
11
and resistance.
For example, when p-type extension areas
16
are formed in p-channel MOS transistor
10
as described above, acceleration voltage for ion implantation is decreased to approximately 0.5 (kV), and the depth of extension areas
16
is decreased to approximately 40 (nm) at present. In extension areas
16
with such an extremely small depth of the junctions, the aforementioned decrease in temperature at low speed leads to considerable variations in depth of the junctions.
The aforementioned problem also occurs in an n-channel MOS transistor (not shown) including n-type extension areas
16
, and occurs whether or not silicon substrate
11
to be annealed has a cover film (not shown) such as a silicon oxide film o
Hayes & Soloway P.C.
Luk Olivia T
NEC Corporation
Niebling John F.
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