Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-07-22
2008-07-22
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S500000
Reexamination Certificate
active
11025196
ABSTRACT:
A circuit for testing a power down reset function of an electronic device includes a reference power source (Vref), a first variable resistor (R1) with one end connected to the reference power source, a second variable resistor (R2), and a jumper (10). One end of the second variable resistor is connected to the other end of the first variable resistor, and the other end of the second variable resistor is grounded. The jumper includes four pins, with a first pin (101) connected to a node (B) between the first variable resistor and the second variable resistor, a third pin (103) grounded, and a second pin (102) and a fourth pin (104) commonly connected to a voltage testing pin (20) of an electronic device (2). The circuit is simple, is conveniently operated, and saves costs.
REFERENCES:
patent: 4471418 (1984-09-01), Tuma
patent: 5047987 (1991-09-01), Kosuge
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patent: 5450417 (1995-09-01), Truong et al.
patent: 6943596 (2005-09-01), Slamowitz et al.
patent: 2001/0020670 (2001-09-01), Hyoga et al.
patent: 2003/0236928 (2003-12-01), Wang et al.
Britt Cynthia
Gandhi Dipakkumar
Morris Manning & Martin LLP
Tingkang Xia, Esq. Tim
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