Circuit for temperature and beta compensation

Details Circuit for temperature and beta compensation Circuit for temperature and beta compensation

2007-04-10

2007-04-10

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C326S126000

Reexamination Certificate

active

10934290

ABSTRACT:
A compensation circuit is disclosed. The compensation circuit includes a driver stage having an output, a differential output device including a base coupled to the output of the driver stage, and a feedback block coupled to a first emitter of the differential output device. The differential output device includes a second emitter to provide a differential output, and the feedback block generates a feedback signal to adjust the differential output. The first emitter comprises a replicating transistor, and is proximate to the second emitter of the differential output device. By keeping the replicating emitter near the differential output device, the variances of temperature and process over the semiconductor die do not affect the performance of the compensation circuit. The compensation circuit may also compensate for variations in common-emitter current gain.

REFERENCES:
patent: 4533842 (1985-08-01), Yang et al.
patent: 5072136 (1991-12-01), Naghshineh
patent: 5124580 (1992-06-01), Matthews et al.
patent: 5994923 (1999-11-01), Navabi
patent: 6104231 (2000-08-01), Kirkpatrick, II
patent: 6104232 (2000-08-01), Filip
patent: 6123107 (2000-09-01), Selser et al.
patent: 6237394 (2001-05-01), Harris et al.
patent: 6297685 (2001-10-01), Ewen et al.
patent: 6366159 (2002-04-01), Taheri
patent: 6434420 (2002-08-01), Taheri
patent: 6434421 (2002-08-01), Taheri
patent: 6438413 (2002-08-01), Taheri
patent: 6445240 (2002-09-01), Taheri
patent: 6608515 (2003-08-01), Taheri
Cypress Advance Information, FastEdge™ Series CS6160ATT, 1 of 2:4 Differential Fanout Buffer, Document #: 38-07551 Rev.**, Revised Jun. 4, 2003.
Cypress Preliminary, FastEdge™ Series CY2DP314, 1 of 2:4 Differential Fanout Buffer, Document #:38-07550 Rev. *B, Revised Feb. 17, 2004.
Cypress, FastEdge™ Series CY2DP3120, 1:20 Differential Fanout Buffer, Document #:38-07514 Rev. *B, Revised May 26, 2004.
Cypress, FastEdge™ Series CY2PP3220, Dual 1:10 Differential Fanout Buffer, Document #:38-07513 Rev. *B, Revised May 26, 2004.
Cypress Advance Information, CY2XP304, High-Frequency Programmable PECL Clock Generation Module, Document #:38-07589 Rev. **, Revised Nov. 25, 2003.
Cypress, FastEdge™ Series CY2PP3210, Dual 1:5 Differential Fanout Buffer, Document #:38-07508 Rev. *B, Revised May 26, 2004.
Cypress Preliminary, FastEdge™ Series CY2PP326, 2×2 Clock and Data Switch Buffer, Document #:38-07506 Rev. *B, Revised Sep. 8, 2003.
Cypress, FastEdge™ Series CY2PP318, 1 of 2:8 Differential Fanout Buffer, Document #:38-07501 Rev. *D, Revised May 26, 2004.

Affiliated with

Also associated with

Rating

Circuit for temperature and beta compensation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit for temperature and beta compensation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for temperature and beta compensation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3748216