Circuit for sensing back-bias level in a semiconductor memory de

Details Circuit for sensing back-bias level in a semiconductor memory de Circuit for sensing back-bias level in a semiconductor memory de

1991-09-16

1993-11-16

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

365159, 331 64, G11C 1300

Patent

active

052629899

ABSTRACT:
A back-bias level sensor used for a semiconductor device wherein a sensing current for sensing a back-bias voltage is prevented from directly flowing into the substrate (or the back-bias voltage terminal). The gate of a PMOS transistor is provided with the back-bias voltage while the source is provided with a ground voltage, so that a pump circuit performs the pumping operation to increase the back-bias voltage when the back-bias voltage is lower than a predetermined voltage level; otherwise, the pump circuit is de-energized, thereby reducing the back-bias voltage.

REFERENCES:
patent: 5138190 (1992-08-01), Yamazaki et al.

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