Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
1999-12-09
2001-03-06
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Precharge
C365S189110
Reexamination Certificate
active
06198680
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a circuit and a method for resetting a pair of data buses.
FIG. 1
is a schematic diagram of a part of a conventional semiconductor memory device
1
comprising a memory cell array
4
including a plurality of memory cells c, a plurality of word lines (not shown) and a plurality of bit line pairs BL
1
, /BL
1
to BLn, /BLn. Each cell c is connected to one of the plurality word lines and also to one of bit lines of any pair BL
1
, /BL
1
to BLn, /BLn. Only three pairs of bit lines, designated as first, second and third line pairs BL
1
, /BL
1
; BL
2
, /BL
2
; and BL
3
, /BL
3
are shown in FIG.
1
.
Sense amps
2
a
,
2
b
and
2
c
are connected between the first, second and third bit line pairs BL
1
, /BL
1
; B
12
, /BL
2
; and BL
3
, /BL
3
, respectively. Each of the sense amps
2
a
to
2
c
amplifies a potential difference between the associated one of the first, second and third bit line pairs BL
1
, /BL
1
to BL
3
, /BL
3
. The bit lines pairs BL
1
to BL
3
and /BL
1
to /BL
3
are also connected to a pair of data buses DB, /DB via pairs of transfer gates
3
a
to
3
c
, respectively. Each pair of transfer gates
3
a
to
3
c
includes a pair of NMOS transistors having gates which receive a common column select signal col
1
to col
3
. When the column select signal col
1
, for example, goes high, the transfer gates
3
a
are turned on, thus electrically connecting the first bit line pair BL
1
, /BL
1
to the data buses DB, /DB.
In a write operation, write data from a write amplifier is written in the memory cell c via the data buses DB, /DB, the transfer gates
3
a
and the first bit line pair BL
1
, /BL
1
. In a read operation, data stored in the memory cell c is read via the first bit line pair, BL, /BL
1
, the transfer gates
3
a
and the data buses DB, /DB to a read amplifier (not shown).
A reset circuit
50
(
60
) is connected between the data buses DB, /DB. The reset circuit
50
of a first prior art example is shown in FIG.
2
(
a
) and the reset circuit
60
of a second prior art example is shown in FIG.
3
(
a
). Each reset circuit
50
or
60
receives a reset control signal &phgr;eq which transitions in the manners illustrated in FIG.
2
(
b
) and
3
(
b
). The reset circuit
50
or
60
resets the potential difference between the data buses DB, /DB in response to the high reset control signal &phgr;eq applied subsequent to a write operation or a read operation.
As shown in FIG.
2
(
a
), the reset circuit
50
comprises three NMOS transistors Q
51
, Q
52
and Q
53
. The NMOS transistor Q
51
is connected between the data buses DB, /DB, and the NMOS transistors Q
52
and Q
53
are connected in series between the data buses DB, /DB. A precharge voltage equal to about half of a high potential power supply Vdd (i.e., Vdd/
2
) is applied to a node between the NMOS transistors Q
52
and Q
53
. The transistors Q
51
to Q
53
have their gates connected together and receive the reset control signal &phgr;eq.
When the NMOS transistors Q
51
to Q
53
are turned on in response to the high reset control signal &phgr;eq, the potentials on the data buses DB, /DB are equalized to Vdd/
2
as illustrated in FIG.
2
(
b
), thus resetting the potential difference between the data buses DB, /DB. By the Vdd/
2
equalization, a power consumption of the reset circuit
50
is reduced.
As shown in FIG.
3
(
a
), the reset circuit
60
comprises an NMOS transistor Q
61
, two PMOS transistors Q
62
and Q
63
and an inverter circuit
61
. The NMOS transistor Q
61
is connected between the data buses DB, /DB, and the PMOS transistors Q
62
and Q
63
are connected in series between the data buses DB, /DB. A precharge voltage having a level equal to a high potential power supply Vdd is applied to a node between the transistors Q
62
and Q
63
. A reset control signal &phgr;eq is applied to the gate of the transistor Q
61
. The reset control signal &phgr;eq inverted by the inverter circuit
61
is applied to the gates of the PMOS transistors Q
62
and Q
63
.
When the NMOS transistor Q
61
and the PMOS transistors Q
62
and Q
63
are turned on in response to the high reset control signal &phgr;eq, the potentials on the data buses DB, /DB are equalized to the high potential power supply level Vdd as illustrated in FIG.
3
(
b
), thus resetting the potential difference between the data buses DB, /DB. Accordingly, if the next cycle is a read cycle, a difference between the potential on any bit line BL
1
, /BL
1
to BL
3
, /BL
3
corresponding to data read from the memory cell c and the potential on the data bus DB or /DB will increase to the supply Vdd level. This improves the charge transfer rate through the associated transfer gate
3
a
to
3
c
and reduces the time t1 required until the potential on the data bus DB or /DB is determined. Thus, the read operation is accelerated in the semiconductor memory device
1
using the reset circuit
60
.
Since the reset circuit
50
equalizes the potentials on the data buses DB, /DB to the Vdd/
2
during the reset operation, a read operation is slow. During the read operation, there is a small difference (Vdd/
2
) between the potential on any of the first to the third bit line BL
1
, /BL
1
to BL
3
, / BL
3
corresponding to data read from the memory cell c and the potential on the data bus DB or /DB. This slows down the charge transfer rate through the transfer gate
3
a
to
3
c
, resulting in a relatively long time t2 until the potential on the data buses DB, /DB is determined, as illustrated in FIG.
2
(
b
).
Since the reset equalizes the potentials on the data buses DB, /DB to Vdd level during the reset operation, power consumption is increased. A write amplifier generally has a greater driving capability than the sense amps
2
a
to
2
c
in order to facilitate the charge/discharge process of the data buses and the first to the third bit line pair. An increased power consumption accrues during the reset operation of the write cycle when equalizing the data buses to the Vdd level.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a reset circuit of a semiconductor memory device which enables a higher rate of operation and reduced power consumption.
In a first aspect of the present invention, a semiconductor memory device including a data bus pair is provided. A first reset circuit is connected between the data buses of the data bus pair and resets the data buses to a first potential. A second reset circuit is connected between the data buses of the data bus pair and resets the data buses to a second potential. A control circuit is connected to the first and second reset circuits, activates the first reset circuit, and deactivates the second reset circuit prior to a write operation. The control circuit deactivates the first reset circuit and activates the second reset circuit prior to a read operation.
In a second aspect of the present invention, a semiconductor memory device including a data bus pair. A reset circuit is connected between the data buses of the data bus pair and resets the data buses to one of a high potential power supply voltage and a low potential power supply voltage. A control circuit is connected to the reset circuit, activates the reset circuit prior to a read operation, and deactivates the reset circuit when a write operation is performed.
In a third aspect of the present invention, a method of resetting a pair of data buses in a semiconductor memory device is provided. The memory device includes a first reset circuit connected between the data buses for resetting the data buses to a first potential and a second reset circuit connected between the data buses for resetting the data buses to a second potential. The method includes the steps of activating the first reset circuit and deactivating the second reset circuit prior to a write operation and deactivating the first reset circuit and activating the second reset circuit prior to a read operation.
In a fourth aspect of the present in
Furuyama Takaaki
Sugamoto Hiroyuki
Arent Fox Kintner & Plotkin & Kahn, PLLC
Elms Richard
Fujitsu Limited
Phung Anh
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