Circuit for reducing the loading effect of an insulated-gate fie

Details Circuit for reducing the loading effect of an insulated-gate fie Circuit for reducing the loading effect of an insulated-gate fie

1979-12-28

1981-07-28

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Precharge

307DIG1, 365156, 365190, G11C 700, G11C 1140

Patent

active

042814006

ABSTRACT:
A charge is placed on the floating substrate of an insulated-gate field-effect transistor IGFET by applying, to the source of the IGFET, a signal making a first transition between first (V.sub.1) and second (V.sub.2) voltages and a second transition between the second voltage and a third voltage (V.sub.3) which is intermediate V.sub.1 and V.sub.2. The first transition is of a polarity and magnitude to forward bias the source-to-substrate junction of the IGFET and establishes a first level (L.sub.1) at the substrate region close to said second voltage. The second transition causes the source potential to go to V.sub.3 but the source-to-substrate junction is reverse biased and the substrate potential remains at a level (L.sub.2) which is intermediate L.sub.1 and V.sub.3. Consequently, the source to substrate junction remains isolated for values of signals applied to the source in the range between V.sub.1 and L.sub.2.

REFERENCES:
patent: 3617775 (1971-11-01), Allen
patent: 3618053 (1971-11-01), Hudson et al.
patent: 4189782 (1980-02-01), Dingwall
Chu et al., Writing FET Memory Cells with Precharged Bit Line, IBM Tech. Disc. Bul., vol. 18, No. 6, 11/75, pp. 1843-1844.

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