Circuit for providing isolation of integrated circuit active...

Details Circuit for providing isolation of integrated circuit active... Circuit for providing isolation of integrated circuit active...

1998-07-29

2002-11-05

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S238000, C438S294000, C438S439000, C438S454000

Reexamination Certificate

active

06475851

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and apparatus for isolating active areas of semiconductor circuitry, and in particular to the use of a grounded gate between such active areas.
BACKGROUND OF THE INVENTION
In the formation of semiconductor chip circuitry such as sources and drains of field effect transistors, it is important that the active areas of the transistors be separated so that electrical current does not flow between them in an unintended manner. Active areas of a transistor are defined as the areas of a transistor where current flows, such as the source and drain of an insulated gate field effect transistor. It is desirable to place unassociated transistors as close together as possible to minimize the total chip area taken up by the transistors. As the space between unassociated transistors shrinks, there is still a need to maintain total electrical isolation between the unassociated transistors. Prior solutions have relied on thick field oxides to achieve isolation, as seen in prior art FIG.
1
.
One problem with the use of field oxide isolation to provide isolation of active areas of adjacent unassociated transistors arises during formation of the oxide layer. When the oxide is formed, it has the tendency to creep under a masking nitride layer, toward the gates of the unassociated transistors. Any misalignment of the gates with respect to the oxide layer causes unbalancing of the transistors, especially when trying to obtain close spacing to conserve real estate on the chip. This unbalancing is the result of one active area being larger than the other active area, and exhibiting different resistance and capacitance. To minimize such problems, the distance between the transistors is increased, resulting in less efficient use of the chip. In dynamic random access memory chips, both efficient use of chip space, and precisely balanced circuits, such as are used in sense amplifiers are critical as the memory capacity of such chips increases.
There is a need to provide effective isolation of unassociated circuitry using as little chip real estate as possible while at the same time providing precisely balanced circuitry.
SUMMARY OF THE INVENTION
An isolating gate is formed between two unassociated transistors in a semiconductor device to provide electrical isolation between the two transistors. The gate is biased to ensure that the field effect transistor formed between the active areas of the adjacent transistors is in an off condition. Keeping the isolating gate biased off takes advantage of the self isolating features of enhancement mode field effect transistors, and provides isolation with much less distance required between the active areas of the adjacent transistors. Since the active transistor gates and the isolation gate are formed at the same time, no misalignment occurs, unlike prior field oxide isolation techniques, where the isolation and transistor gates are formed using separate masks which are easily misaligned. This in turn provides the ability to provide a higher density of transistors on a given semiconductor die. The transistors are much more precisely balanced due to the use of the single mask to form all the gates. In addition, fewer process steps are required to provide the semiconductor device.
In one embodiment, the transistors comprise n-channel insulated gate field effect transistors. The isolating gate is coupled to ground. In a further embodiment, the transistors comprise p-channel insulated gate field effect transistors having the isolating gate coupled to Vcc. In both such embodiments, the isolating gate is held in an off condition by the reference voltage to provide effective isolation of the unassociated transistors.
In a further embodiment, pairs of transistors form sense amplifiers for dynamic random access memory devices. A first pair of transistors is isolated by the isolating gate from a second pair. Sense amplifiers are cross coupled enhancement mode field effect transistors, and the pair of transistors must be precisely balanced and isolated from other sense amplifiers in order to provide correct sensing of memory cells in the memory device. The present invention provides the ability to pack sense amplifiers closer together while still providing effective isolation and not adversely affecting the balanced relationship between the transistors forming the sense amplifiers.


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