Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-02-08
2003-01-21
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S112000, C327S309000
Reexamination Certificate
active
06509760
ABSTRACT:
The present invention relates to a circuit and in particular, but not exclusively for use as an output buffer which drives a high voltage field effect transistor.
A simple output buffer is shown in FIG.
1
. In this known circuit, the supply voltage V
DD
is assumed to be less than the maximum gate to source voltage V
GS
of a switching PMOS transistor A. A first and a second switching transistor
2
and
4
are connected in series. The first transistor
2
is a P channel field effect transistor with its source connected in series to the drain of the second transistor
4
which is an N channel field effect transistor. The source of the N channel transistor
4
is connected to ground and the source of the P channel transistor
2
is connected to the supply voltage V
DD
. The drain of the P channel transistor
2
and the drain of the N channel transistor
4
are connected to a load
6
. The load
6
(which represents the gate of the switching transistor A) in this case is represented by a capacitive load connected between the drain of the N channel transistor
4
and the ground.
The gates of both the N channel transistor
4
and the P channel transistor
2
are connected to a respective control voltage V
i
′ and V
i
. V
i
′ and V
i
have the same logic value. In other words, V
i
′ and V
i
are usually logic level high or low at the same time and usually change state at the same time. V
i
′ and V
i
, are often generated separately. The control circuitry which controls the signals V
i
′ and V
i
is well-known and, therefore, is not shown. Unless otherwise stated, V
i
′ and V
i
will be generically called V
i
hereinafter.
When V
i
is in a logic low state, the P channel transistor
2
is switched on and the N channel transistor
4
is switched off. This allows current to flow into the load
6
from the supply V
DD
via the first P channel transistor
2
. This current is termed source current. As the source current flows, the voltage developed across the load
6
increases. The source current will flow whilst there is potential difference between the supply and load
6
. In other words, the source current will stop flowing when the supply voltage V
DD
is equal in magnitude to the voltage across the load
6
. At this time, the current supplied by the supply V
DD
will be zero.
When V
i
is in a logic high state, the N channel transistor
4
is switched on and the P channel transistor
2
is switched off. This allows current to flow from the load
6
through the N channel transistor
4
to ground. This current is termed sink current. As the sink current flows out of the load
6
to ground, the voltage developed across the load
6
drops. The sink current flows until the voltage developed across the load
6
is equal to zero volts.
One problem with the circuit shown in
FIG. 1
is that in high voltage situations, the supply voltage V
DD
cannot be assumed to be less than the maximum gate to source voltage of the P channel transistor A. In this case, additional circuitry is added between the load
6
and the supply voltage V
DD
. This additional circuitry needs to maintain a voltage between the drain and source of the P channel transistor A, which is equal to or less than the maximum gate to source voltage of the P channel transistor A. This additional circuitry is called a voltage clamp
8
and is shown in FIG.
2
.
With the addition of the voltage clamp
8
between the load
6
and the supply voltage V
DD
, the minimum output voltage which can be developed across the load
6
, will be the difference between the supply voltage V
DD
and the voltage V
CLAMP
which is dropped across the clamp
8
.
With the circuit shown in
FIG. 2
, when V
i
is in a low logic state, the P channel transistor
2
is switched on and the N channel transistor
4
is switched off. The source current will flow from the supply V
DD
, through the P channel transistor
2
and into the load
6
. As the source current flows into the load
6
, the voltage developed across the load
6
increases. When the voltage developed across the load
6
reaches a value which is equal in magnitude to the supply voltage V
DD
, the source current will cease flowing.
When V
i
is in a high logic state, the N channel transistor
4
is switched on and the P channel transistor
2
is switched off. The load
6
will now begin to discharge through the N channel transistor
4
to ground. As the load
6
discharges, the voltage across the load
6
decreases. When the load
6
reaches a value which is equal in value to the difference between the supply voltage V
DD
and the clamp voltage V
CLAMP
, the sink current, which was supplied from the load
6
, is now supplied by the supply voltage V
DD
and flows through the clamp
8
. The sink current flows from the supply V
DD
through the N channel transistor
4
to ground until V
i
changes to a low logic state. V
i
changing to a low logic state switches the P channel transistor
2
on and the N channel transistor
4
off.
This excess sink current flowing from the supply V
DD
leads to an excessively high power dissipation within the circuit and this increased power dissipation is currently taken into account when designing an output buffer. The excess power dissipation is due to sink current flowing from the voltage supply V
DD
through the clamp
8
and the N channel transistor
4
to ground after the voltage of the load
6
reaches the value of V
DD
−V
CLAMP
. This power dissipation is disadvantageous because it increases power consumption within the circuit.
It is an aim of embodiments of the invention to address the disadvantages of the known arrangements, and reduce the power dissipation.
According to a first aspect of the invention, there is provided a circuit for providing a control signal for a load comprising a first switch having a first and a second state, a second switch having a first and a second state coupled to said first switch; a load connected to said first and second switches; protection circuitry for protecting said load from excessive voltage; and circuitry for switching said first switch, said circuit being arranged so that when said first switch is in the first state, current flows from the load to said first switch, said switching circuitry being arranged to switch said first switch to said second state when the voltage across the load reaches a predetermined value.
REFERENCES:
patent: 4612457 (1986-09-01), Prater
patent: 5117129 (1992-05-01), Hoffman et al.
patent: 5179300 (1993-01-01), Rolandi et al.
patent: 5426383 (1995-06-01), Kumar
patent: 5432463 (1995-07-01), Wong et al.
patent: 5440182 (1995-08-01), Dobbelaere
patent: 5442304 (1995-08-01), Wong et al.
patent: 5568068 (1996-10-01), Ota et al.
patent: 6100718 (2000-08-01), Blaud et al.
patent: 63119323 (1988-05-01), None
Standard Search Report from the British priority application filed Feb. 15, 2000.
Patent Abstracts of Japan, vol. 012, No. 367 (E-664), Sep. 30, 1988 & JP 63 119323 May 24, 1988.
Patent Abstracts of Japan, vol. 015, No. 139 (E-1053), Aug. 15, 1995 & JP 03 019423 Jan. 28, 1991.
Cho James A
Morris James H.
Skrivanek, Jr. Robert A.
STMicroelectronics Limited
Tokar Michael
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