Circuit for PLL-based at-speed scan testing

Details Circuit for PLL-based at-speed scan testing Circuit for PLL-based at-speed scan testing

2008-05-27

2008-05-27

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000

Reexamination Certificate

active

10868546

ABSTRACT:
A scheme for PLL-based at-speed scan testing in which a clock generation circuit is used to generate different clock signals to scannable flip-flops of an integrated circuit. When the integrated circuit is under at-speed scan test mode of operation, the clock generation circuit receives a scan-clock signal to scan in a test vector to the scannable flip-flops during an input shift phase when shifting is enabled and to scan out a resultant vector from the scannable flip-flops during an output shift phase when shifting is also enabled. However, when shifting is not enabled during a capture phase between the two shift phases, the scan-clock signal triggers a 2-pulse circuit to release two pulses during the capture phase of at-speed scan testing. The two pulses from the 2-pulse circuit are based on an internal PLL-based clock signal. The clock generation circuit may be utilized in single or multiple clock domain systems. In a multiple clock domain environment, separate scan-clock signals may be sent to individual clock domains within an integrated circuit and only the domain to be acted on by a test vector has its respective scan-clock pulsed during the capture phase.

REFERENCES:
patent: 6598192 (2003-07-01), McLaurin et al.
patent: 6966021 (2005-11-01), Rajski et al.
patent: 7155651 (2006-12-01), Nadeau-Dostie et al.
“A Novel and Practical Scheme for Inter-Clock At-Speed Testing” by Hiroshi Furukawa This paper appears in: IEEE International Test Conference, 2006. ITC '06. Publication Date: Oct. 2006, pp. 1-10, ISSN: 1089-3539, ISBN: 1-4244-0292-1, INSPEC Accession No: 9297790.
“PLL based high speed functional testing” by Jayabalan et al. This paper appears in: 12th Asian Test Symposium, 2003. ATS 2003. Publication Date: Nov. 16-19, 2003 on pp. 116-119, ISSN: 1081-7735, ISBN: 0-7695-1951-2, INSPEC Accession No. 7905566.
N. Tendolkar et al.; Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microporcessors Based on Power PC Instruction Set Architecture Proceedings of the IEEE VLSI Test Symposium 2002.
X. Lin et al.; “High-Frequency, At-Speed Scan Testing”; IEEE Design & Test of Computers, Sep.-Oct. 2003; pp. 17-25.

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