Circuit for performing a parallel write test of a wide multiple

Static information storage and retrieval – Read/write circuit – Testing

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36518904, G11C 2900

Patent

active

052028534

ABSTRACT:
A multiple byte wide parallel write circuit having a number of cell array blocks for storing data, and a plurality of data input buffers includes a plurality of data bus selectors for selecting data buses, a plurality of clock pulse generators for generating clock signals for an individual data input driver on the basis of a test mode enable signal and a column/row address signal, and a plurality of individual data input drivers for driving respective outputs of the data bus selectors and for applying the output driven to the entire input/output (I/O) lines at the same time. Thereby, the improvement may write into the memory cell arrays the data having a greater number of bit lines than that of the data buses, without increasing the layout area nor increasing the load on the bus lines.

REFERENCES:
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patent: 4873669 (1989-10-01), Furutani et al.
patent: 4881200 (1989-11-01), Urai
patent: 4899313 (1990-02-01), Kumanoya et al.
patent: 4907203 (1990-03-01), Wada et al.
patent: 4965769 (1990-10-01), Etoh et al.

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