Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-08-14
2004-01-06
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189020, C326S086000, C326S087000, C327S108000
Reexamination Certificate
active
06674671
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of circuits for handling multiple possible drivers of a line.
2. Description of the Related Art
In circuit design, there are many uses for a line (or buses comprising multiple lines) which may have multiple drivers of the line. Generally, one of the drivers may drive the line at any given time. For example, memory arrays such as caches may employ such a structure for each bit read from the memory array. The memory array may include multiple banks, one of which may be read at any given time. Each bank has an output that may drive the line corresponding to the bit, and the bank that is being read drives the line. As another example, communication lines between two or more circuits may be driven by any of the circuits according to some protocol (often referred to as bi-directional lines, since the lines may be inputs or outputs of a given circuit at a given point in time).
FIG. 1
illustrates a first prior art circuit providing for multiple drivers of a line (the line is illustrated as carrying a D
out
signal in
FIG. 1
, and may be referred to herein as the D
out
line). The circuit of
FIG. 1
may sometimes be referred to as a low swing, dual rail dynamic circuit. Each driver may drive a dynamic data signal and its complement (e.g. the dynamic data signal d
0
and its complement d
0
# may be driven by a first driver and the dynamic data signal d
1
and its complement d
1
# may be driven by a second driver). In
FIG. 1
, the dynamic data signals are precharged low and conditionally evaluate high dependent on whether or not the driver is driving a value and whether or not the value is a logical one or a logical zero. At most one driver may be permitted to drive its dynamic data signals at any given evaluation of the D
out
signal. For example, the driver corresponding to the dynamic data signals d
0
and d
0
# may drive the line. If the value being driven is a logical one, the d
0
dynamic data signal may assert. If the value is a logical zero, the d
0
# dynamic data signal may assert. Each dynamic data signal is coupled to the gate of an n-type metal oxide semiconductor (NMOS) transistor which is further coupled to one of two bit lines (bit and bit#). The bit and bit# lines are precharged to V
dd
using the PMOS transistors coupled to the precharge signal Pchg. One of the bit and bit# lines may be conditionally discharged by an NMOS transistor receiving an asserted dynamic data signal. A pair of PMOS transistors having gates coupled to bit and bit# lines and coupled to the opposite bit or bit# line may actively hold the precharge on the bit or bit# line which is not discharged by the NMOS transistors, responsive to the discharge of the bit or bit# line to which its gate is coupled. A sense amplifier (SA) is coupled to the bit and bit# lines and senses the differential between the two lines (responsive to the clock input SACLK) to generate the output line (D
out
). Two additional NMOS transistors may be added for each additional driver (having gates coupled to receive the dynamic data signal and its complement from that driver).
FIG. 2
illustrates a second prior art circuit which may be used to handle multiple drivers of a line (D
out
). The circuit of
FIG. 2
may sometimes be referred to as a single-rail dynamic circuit. In
FIG. 2
, each driver may drive a dynamic data signal (e.g. the dynamic data signal d
0
may be driven by a first driver and the dynamic data signal d
1
may be driven by a second driver). Similar to
FIG. 1
, the dynamic data signals are precharged low in this embodiment and conditionally evaluate high if the corresponding driver is driving D
out
and the value being driven is a binary one. Each dynamic data signal is coupled to the gate of an NMOS transistor, which discharges the internal node N
1
in response to the dynamic data signal asserting. A precharge PMOS transistor is coupled to the node N
1
and precharges the node N
1
to V
dd
responsive to the precharge signal Pchg. An inverter is coupled between the node N
1
and the output D
out
, and a feedback PMOS transistor has a gate terminal coupled to D
out
and coupled to the node N
1
to maintain the precharge state if the NMOS transistors do not discharge the node N
1
. Thus, an output D
out
of binary zero is supplied via the precharge if there are no drivers or if the driver is driving a binary zero (and thus does not assert its dynamic data signal). An output D
out
of binary one is supplied if the driver is driving a binary one (and thus asserts its dynamic data signal). Each additional driver may be handled by adding an NMOS transistor in parallel with those shown in FIG.
2
and coupled to receive the dynamic data signal from the additional driver.
FIG. 3
illustrates a third prior art circuit which may be used to handle multiple drivers of a line (D
out
). The circuit of
FIG. 3
may sometimes be referred to as a static push/pull circuit. The circuit of
FIG. 3
takes static inputs (the complement of the data being driven, d
0
# or d
1
#, and a select line sel
0
or sel
1
) from each potential driver of the line. The driver of the line asserts its select line sel
0
or sel
1
and provides the data to be driven on the complement data signal d
0
# or d
1
#. The first driver (d
0
# and sel
0
) is handled via a NAND gate
10
, a PMOS transistor
12
, a NOR gate
16
, and an NMOS transistor
18
. The NAND gate
10
is coupled to receive the sel
0
signal and the d
0
# signal, and is coupled to the gate of a PMOS transistor
12
, which is coupled to the input of an inverter
14
. The NOR gate
16
is coupled to receive the sel
0
signal (on an inverting input) and the d
0
# signal, and is coupled to the gate of the NMOS transistor
18
, which is coupled to the input of the inverter
14
. If the d
0
# signal is a one (the data is a zero) and the select signal is a one, the NAND gate
10
activates the PMOS transistor
12
, driving the input of the inverter
14
to a one and thus D
out
to a zero. If the d
0
# signal is a zero and the select signal is a one, the NOR gate
16
activates the NMOS transistor
18
, driving the input of the inverter to a zero and thus D
out
to a one. If the select line is a zero, then neither of the PMOS or NMOS transistors
12
or
18
is activated. A similar circuit handles the second driver (d
1
# and sel
1
), and additional circuits may be added to handle additional drivers.
FIG. 4
illustrates a fourth prior art circuit which may be used to handle multiple drivers of a line (D
out
). The circuit of
FIG. 4
may sometimes be referred to as static tristate inverters. A first tristate inverter corresponds to the first driver (d
0
and sel
0
) and includes PMOS transistors
20
and
22
in a stack and NMOS transistors
24
and
26
in a stack. The PMOS transistor
20
has its gate coupled to the d
0
signal, while the PMOS transistor
22
has its gate coupled to receive the inverse of the sel
0
signal. The NMOS transistor
24
has its gate coupled to receive the sel
0
signal, and the NMOS transistor
26
has its gate coupled to the d
0
signal. Essentially, the transistors
22
and
24
activate if the sel
0
signal is asserted, and one of the transistors
20
or
26
activates in response to the data signal d
0
. Thus, either a binary zero is driven on D
out
by transistors
20
and
22
through the inverter
28
if the sel
0
signal is asserted and d
0
is a zero, or a binary one is driven on D
out
by transistors
24
and
26
through the inverter
28
if the sel
0
signal is asserted and d
0
is a one. If the sel
0
signal is deasserted, then the tri-state inverter does not drive the inverter
28
. A similar circuit is used for the second driver (d
1
and sel
1
), and additional circuits may be added to handle additional drivers.
SUMMARY OF THE INVENTION
In one embodiment, an apparatus includes at least a first transistor, a second transistor, and a circuit. The first transistor ha
Campbell Brian J.
Do Tuan P.
Broadcom Corp.
Mai Son
Merkel Lawrence J.
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