Circuit for high speed dynamic memory

Details Circuit for high speed dynamic memory Circuit for high speed dynamic memory

2011-08-30

2011-08-30

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S145000

Reexamination Certificate

active

08009459

ABSTRACT:
A memory cell includes a write access transistor coupled between a storage node and a write bit line, and active during a write cycle responsive to a voltage on a write word line; a read access transistor coupled between a read word line and a read bit line, and active during a read cycle responsive to a voltage at the storage node; and a storage capacitor coupled between the read word line and the storage node. Methods for operating the memory cell are also disclosed.

REFERENCES:
patent: 3387286 (1968-06-01), Dennard
patent: 4935896 (1990-06-01), Matsumura et al.
patent: 5646903 (1997-07-01), Johnson
patent: 6101117 (2000-08-01), Tiwari
patent: 6314017 (2001-11-01), Emori et al.
patent: 6804142 (2004-10-01), Forbes
patent: 6982897 (2006-01-01), Luk et al.
patent: 7016234 (2006-03-01), Ishida et al.
patent: 7440334 (2008-10-01), Barth et al.
Ekanayake, V. N., et al.; “Asynchronous DRAM Design and Synthesis”; IEEE Asynchronous Circuits and Systems, 2003 Proceedings, Ninth International Symposium, May 12-15, 2003, pp. 174-183.

Affiliated with

Also associated with

Rating

Circuit for high speed dynamic memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit for high speed dynamic memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for high speed dynamic memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2697202