Circuit for evaluating signal timing

Details Circuit for evaluating signal timing Circuit for evaluating signal timing

1998-05-22

2000-06-06

Nguyen, Hoa

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714724, 714726, 714744, G01R 3128

Patent

active

06073261&

ABSTRACT:
The present invention is generally directed to a circuit and method for evaluating the timing relationship of electrical signals in an integrated circuit. In accordance with one aspect of the invention, a circuit is provided having a signal select circuit that is includes two or more inputs and one output. The signal select circuit (preferably a multiplexer) is configured to select one of the two or more input signals for evaluation and direct it to the output. A plurality of signal buffers are electrically cascaded to the output of the signal select circuit. Finally, a scan chain having a plurality of scan elements is disposed to acquire a state of electrical signals along the plurality of signal buffers. In accordance with another aspect of the invention, a method is provided for evaluating the timing relationship of electrical signals in an integrated circuit. In accordance with this inventive aspect, the method includes the steps of selecting a first electrical signal to be evaluated and discretizing the selected electrical signal into a plurality of signal values closely spaced in time. This "discretizing" function is preferably achieved passing the selected signal through a plurality of cascaded delay or buffer elements, then loading the signal values output from each buffer element (at a given time instance) into a plurality of register elements. In this way, the register elements, collectively, contain a snapshot of the selected signal over a defined period of time. Finally, the method includes the step of evaluating the plurality of signal values.

REFERENCES:
patent: 5208764 (1993-05-01), Rusu et al.
patent: 5384494 (1995-01-01), Henson et al.
patent: 5642362 (1997-06-01), Savir
patent: 5923676 (1999-07-01), Sunter et al.
patent: 5938780 (1999-08-01), Panis

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