Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Patent
1997-09-29
1999-06-29
Mis, David
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
361 56, H02H 904, H01L 2362
Patent
active
059173360
ABSTRACT:
An electrostatic discharge (ESD) circuit (700) provides robust protection to an input/output driver circuit (10). The discharge path is provided by a bipolar transistor (202). The bipolar device is triggered by a combination of an n-type MOSFET (702), a string of diodes (200), and a biasing circuit (704). The trigger point of the MOSFET is programmable by varying the number of individual diodes in the string of diodes. The relatively high transconductance of the n-type MOSFET allows the use of a smaller ESD circuit for a given degree of protection.
REFERENCES:
patent: 5530612 (1996-06-01), Maloney
patent: 5539327 (1996-07-01), Shigehara et al.
patent: 5565790 (1996-10-01), Lee
Naresh Tandan, "ESD Trigger Circuit", EOS/ESD Symposium, Section 3.3.1-3.3.5 (1994).
Voldman et al., "Analysis of Snubber-Clamped Diode-String Mixed Voltage Interface ESD Protection Network for Advanced Microprocessors", EOS/ESD Symposium, pp. 43-61 (1995).
Amerasekera, et al., "Substrate Triggering and Salicide Effects on ESD Performance and Protection Circuit Design in Deep Submicron CMOS Processes", IEDM, pp. 547-550 (1995).
Ramaswamy, et al., "EOS/ESD Analysis of High-Density Logic Chips", EOS/ESD Symposium, pp. 285-290 (1996).
Jamison Stephen G.
Smith Jeremy C.
Chastain Lee E.
Mis David
Motorola Inc.
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