Circuit for efficiently testing memory and shadow logic of a sem

Details Circuit for efficiently testing memory and shadow logic of a sem Circuit for efficiently testing memory and shadow logic of a sem

1998-06-12

2000-07-11

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714727, G01R 3128

Patent

active

060888237

ABSTRACT:
A circuit for efficiently performing shadow logic testing and memory block testing within a semiconductor integrated circuit. The integrated circuit includes a memory block for storing data. A shadow logic circuit is coupled to the memory block for interfacing the memory block with external circuitry. The shadow logic provides inputs to the memory block and receives data outputs from the memory block. A test collar is coupled between the memory block and the shadow logic. The test collar receives the data inputs from the shadow logic and receives the data outputs from the memory block. The test collar is configured to both provide test inputs to the shadow logic and capture test outputs from the shadow logic independent of the memory block. The test collar is also adapted to both provide tests inputs to the memory block and capture test outputs from the memory block independent of the shadow logic. Thus, the built in test circuit of the present invention is able to perform precise isolated testing on the memory block and perform precise isolated testing on the shadow logic.

REFERENCES:
patent: 3961254 (1976-06-01), Cavalier et al.
patent: 4070565 (1978-01-01), Borelli
patent: 4912395 (1990-03-01), Sato et al.
patent: 5805605 (1998-09-01), Lee et al.

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