Circuit for decoding 2T encoded binary signals

Details Circuit for decoding 2T encoded binary signals Circuit for decoding 2T encoded binary signals

1994-12-14

1996-03-26

Westin, Edward P.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

377 73, 377 75, 360 51, 341 50, 341 94, G11C 800

Patent

active

055024084

ABSTRACT:
A decoding circuit for 2T encoded binary signals, comprises: a data input terminal; a first D-type flip flop having an input coupled to the input terminal; a first exclusive OR gate having inputs coupled to the input terminal and an output of the first D-type flip flop; a shift register having an input coupled to an output of the exclusive OR gate; a second D-type flip flop having an input coupled to the shift register; and, a second exclusive OR gate having inputs coupled to an output of the second D-type flip flop and to a tap of the shift register, the second exclusive OR gate having an output at which decoded input signals are reconstituted. The second D-type flip flop may be a constituent stage of the shift register, the inputs of the second exclusive OR gate being coupled to adjacent taps of the shift register. At least one of the adjacent taps is the output of the constituent stage formed by the second D-type flip flop. A gate arrangement is coupled to a plurality of taps of the shift register for decoding a predetermined bit pattern in the input signal, for example, a synchronizing component of a digitally recorded video signal played back to the data input terminal. The consecutive taps of the shift register are chosen for equalizing a delay time between detection of the synchronizing component and the reconstituted video signal.

REFERENCES:
patent: 4055727 (1977-10-01), Katoh
patent: 4594703 (1986-06-01), Tomisawa et al.
patent: 4675884 (1987-06-01), Nakamura et al.
patent: 4837790 (1989-06-01), Harada
patent: 5111486 (1992-05-01), Oliboni et al.

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