Circuit for controlling a self-refresh period in a semiconductor

Details Circuit for controlling a self-refresh period in a semiconductor Circuit for controlling a self-refresh period in a semiconductor

1994-07-14

1996-02-27

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Data refresh

365191, 365233, G11C 1300

Patent

active

054954525

ABSTRACT:
A circuit which controls a self-refresh period of a semiconductor memory device includes a pulse generating circuit which outputs a periodic pulse train in response to an external control signal, a frequency-dividing circuit which outputs a plurality of pulse trains having different respective periods by frequency-dividing the pulse train, at least one temperature detector which detects an ambient temperature of the memory device and outputs a temperature detection signal when the ambient temperature exceeds a predetermined threshold level, at least one voltage detecting circuit which detects a power supply voltage applied to the memory device and outputs a voltage detection signal when the power supply voltage reaches a predetermined level, a combination pulse train generating circuit which outputs a plurality of combination pulse trains by variously combining the plurality of pulse trains output by the frequency-dividing circuit, and a pulse selecting circuit which outputs a self-refresh master clock by selecting one of the combination pulse trains in response to the voltage detection signal and the temperature detection signal.

REFERENCES:
patent: 5337282 (1994-08-01), Koike
patent: 5343430 (1994-08-01), Furuyama
patent: 5349562 (1994-09-01), Tanizaki
patent: 5365487 (1994-11-01), Patel et al.

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