Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-07-09
2002-07-09
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06418546
ABSTRACT:
CROSS REFERENCE TO FOREIGN APPLICATION
This application claims priority based on German Utility Model 198 31 088.9, filed Jul. 10, 1998, the entire disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
The invention relates generally to test circuitry and, particularly, to a circuit arrangement for checking a tristate detection circuit.
In digital technology, for reasons of miniaturization and reducing the number of connections or terminals, a so-called tristate logic is used in which three differentiable logic states can be generated on the terminals. These states are: 1) terminal at logical “1” (supply voltage); 2) terminal at logical “0” (ground); and 3) high-impedance state in which the terminal as such is set to an undefined potential and by means of an additional circuit, it can be set to a potential that is different from the supply voltage and ground. Those skilled in the art employ tristate detection circuits for detecting which of the three states is present.
In safety-related applications (e.g., accident prevention grating, light barriers and the like), in which fail-safe operation is required, it is necessary to check the detection circuit for how it is operating to bring a monitored machine into a safe state in the case of a malfunction of the detection circuit. Therefore, a circuit arrangement is desired for checking a tristate detection circuit to reliably detect all possible errors in the detection circuit.
SUMMARY OF THE INVENTION
The invention meets the above needs and overcomes the deficiencies of the prior art by providing a circuit for checking a tristate detection circuit. Among the several objects and features of the present invention may be noted the provision of such a circuit that permits reliable detection of all possible errors in a tristate detection circuit; and the provision of such a circuit that is economically feasible and commercially practical.
Briefly described, a circuit embodying aspects of the invention simulates the three states of the detection circuit by controllable switches.
According to a preferred embodiment of the invention, a connector that can assume the three states is connected in the middle of a symmetrical voltage divider between supply voltage and ground. The detection circuit has comparators that respond to a voltage drop across resistors of the voltage divider. The controllable switches in the active state connect these resistors and, therefore, a connector of the comparator to ground or to supply voltage, so that regardless of the momentary state to be detected at the connector, the output signal of the comparators will be forced to a defined value (logical “0” or logical “1”). By means of an alternating opening and closing of the individually controllable switches, a change of state will also be created at the output of the comparators. In one test sequence, all permissible combinations of positions of the controllable switches will be run through, so that not only the static state of the output signals of the comparators will be checked, but also their dynamic state, i.e., whether they switch on or off. To increase the fail-safe operation, the circuit arrangement is designed with two channels.
In one embodiment, the voltage divider has four resistors connected in series. The connection to be monitored is connected by a first pair of resistors connected in series to supply voltage, and via a second pair, which is symmetrical to the first, of resistors connected in series to ground. Thus, an electric current flows steadily along the connection, which has the advantage that external switches, which set the connector into the particular electrical state, are always switched under current.
The common node of the resistors of one pair forms a “measured input” of the allocated comparator. This point is forced to supply voltage or to ground by means of the controllable switch, regardless of the state of the connection, since this is “decoupled” electrically from the common node of the resistors of a pair by means of a corresponding resistor.
Preferably, the controllable switches are activated and deactivated alternately in all allowed combinations during a test sequence, so that the comparators have to switch on and also switch off during the course of one complete test cycle. Thus, not only are the states of the individual comparators checked statically, but also a dynamic testing of the changeover of the comparators takes place. Preferably, a test sequence is structured so that after one test phase with an activated, controllable switch, a “read phase” will follow, in which the state of the connection is queried.
The comparators are designed preferably as inverting comparators, that is, at their outputs they have a logical “1” if they have not been “tripped,” i.e., the voltage drop at the resistor allocated to it is below a response threshold, and a logical “0” if they have been tripped, i.e., the voltage drop at the allocated resistor is above the response threshold.
Alternatively, the invention may comprise various other methods and systems.
Other objects and features will be in part apparent and in part pointed out hereinafter.
REFERENCES:
patent: 3764995 (1973-10-01), Helf, Jr. et al.
patent: 5432440 (1995-07-01), Bartlett
patent: 5714892 (1998-02-01), Bowers et al.
patent: 5969540 (1999-10-01), Hwang
patent: 6028443 (2000-02-01), Ozaki
patent: 6133753 (2000-10-01), Thomson et al.
patent: 19736216 (1998-03-01), None
Haberer Hermann
Haberl Paul
Hartl Paul
Chase Shelly A.
De'cady Albert
Kinberg Robert
Leuze lumiflex GmbH & Co.
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