Circuit for charging and discharging a row of memory cells

Details Circuit for charging and discharging a row of memory cells Circuit for charging and discharging a row of memory cells

1986-10-03

1988-03-08

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

365189, 365175, 307296R, G11C 1136, G11C 700, H03K 301

Patent

active

047302780

ABSTRACT:
A circuit is described that provides a quick charge and discharge of a row of memory cells. A first transistor has its collector-emitter path coupled between a first voltage and a row of memory cells, and a base coupled to an input terminal. A second transistor has its collector-emitter path coupled to the first voltage by a resistor and to a voltage level setting device, and a base coupled to the input terminal. A third transistor has its collector-emitter path coupled between the row of memory cells and a second voltage, and a base coupled to a voltage level shifting device. As the row of memory cells are selected, the third transistor becomes less conductive, thereby sinking less current from the row of memory cells and allowing the inherent capacitance of the row of memory cells to charge more quickly. As the row of memory cells are deselected, the third transistor becomes more conductive, thereby sinking more current from the row of memory cells and discharging the inherent capacitance more quickly.

REFERENCES:
patent: 4520462 (1985-05-01), Yamada et al.
patent: 4567381 (1986-01-01), Piasecki
Toyoda et al., "A High Speed 16 Kbit ECL RAM", IEEE Journal of Solid State Circuits, vol. sc-18, No. 5, Oct. 1983, pp. 510-511.

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