Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction
Reexamination Certificate
2007-07-03
2007-07-03
Britt, Cynthia (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Skew detection correction
Reexamination Certificate
active
10873772
ABSTRACT:
A deskewing circuit configured to receive a main clock signal wherein data bits are misaligned with respect to the main clock signal. A multiphase clock generator coupled to the main clock to generate N/2 clock phases on the rising edge of the main clock and N/2 clock phases on the falling edge. A plurality of n samplers to generate a first set of N/2 sampled signals on the positive phases and a second set of N/2 sampled signals on the negative phases. A corresponding plurality of n phase selectors to determine which phase is the best for each set of sampled signals and generate the two selected signals corresponding to that phase. A control logic block configured to receive a corresponding plurality of n first control signals. A data bus gathering all said selected signals for further processing, wherein said selected signals are aligned with said reference clock but misaligned with respect to each other.
REFERENCES:
patent: 6907552 (2005-06-01), Collins
patent: 6990613 (2006-01-01), Doi et al.
patent: 7010729 (2006-03-01), Doi et al.
Buchmann Peter
Nicot Sylvie
Pereira David
Britt Cynthia
Cioffi James J.
Petrokaitis Joseph
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