Circuit for biasing row of memory cells

Details Circuit for biasing row of memory cells Circuit for biasing row of memory cells

1985-12-16

1988-03-08

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, 365179, G11C 700, G11C 800, G11C 1134

Patent

active

047302771

ABSTRACT:
A circuit for selecting a row of memory cells of an array is disclosed that reduces selection time, eliminates the need for providing a regulated voltage for biasing an active load, and utilizes the capacitive charge on the lower word line in the selection of the row. The array includes a first voltage terminal, a second voltage terminal, a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, wherein the plurality of memory cells are arranged in a matrix of rows and columns. Each of the cells in a row are coupled between the first voltage terminal and a word line, and each of the cells in a column are coupled between a pair of the bit lines. A word line driver circuit is coupled between bases of active load transistors in each of the memory cells in a row and the word line of that row for selecting that row of memory cells.

REFERENCES:
patent: 4488268 (1984-12-01), Toyoda
patent: 4601014 (1986-07-01), Kitano et al.
patent: 4627031 (1986-12-01), Van Tran

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