Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-04-22
2008-04-22
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S528000, C324S765010, C326S039000, C326S096000
Reexamination Certificate
active
11064129
ABSTRACT:
According to one aspect of the invention, a circuit for determining the location of a defect in an integrated circuit is described. The circuit comprises a conductor extending from a first node to a second node and a test signal driver coupled to the first node of the conductor. The test signal driver receives a test signal using a first clock signal, while a plurality of detector circuits coupled to the conductor between the first node and the second node to detect an output at the plurality of nodes using a second clock signal. According to other embodiments, circuits for determining the location of a defect in a programmable logic device are disclosed. Finally, various methods for determining the location of a defect in an integrated circuit are described.
REFERENCES:
patent: 4194113 (1980-03-01), Fulks et al.
patent: 5596587 (1997-01-01), Douglas et al.
patent: 5790479 (1998-08-01), Conn
patent: 5963046 (1999-10-01), Konuk
patent: 5976898 (1999-11-01), Marty et al.
patent: 6005829 (1999-12-01), Conn
patent: 6069849 (2000-05-01), Kingsley et al.
patent: 6075418 (2000-06-01), Kingsley et al.
patent: 6122209 (2000-09-01), Pass et al.
patent: 6144262 (2000-11-01), Kingsley
patent: 6157210 (2000-12-01), Zaveri et al.
patent: 6219305 (2001-04-01), Patrie et al.
patent: 6232845 (2001-05-01), Kingsley et al.
patent: 6233205 (2001-05-01), Wells et al.
patent: 6278291 (2001-08-01), McClintock et al.
patent: 6425077 (2002-07-01), Le et al.
patent: 6452459 (2002-09-01), Chan et al.
patent: 6466520 (2002-10-01), Speyer et al.
patent: 6477115 (2002-11-01), Inoshita et al.
patent: 6509739 (2003-01-01), Voogel et al.
patent: 6530071 (2003-03-01), Guccione et al.
patent: 6536007 (2003-03-01), Venkataraman
patent: 6570181 (2003-05-01), Graas et al.
patent: 6574761 (2003-06-01), Abramovici et al.
patent: 6691267 (2004-02-01), Nguyen et al.
patent: 6775817 (2004-08-01), Ono et al.
patent: 6817006 (2004-11-01), Wells et al.
Mark et al., Localizing Open Interconnect Defects using Targeted Routing in FPGA's, Feb. 2004, IEEE, Paper 22.1, pp. 627-634.
U.S. Appl. No. 10/703,326, filed Nov. 7, 2003, Mark et al.
U. S. Appl. No. 10/280,611, filed Oct. 25, 2002, Mark et al.
Fan Yuezhen
Mark David
Britt Cynthia
King John J.
Tabone, Jr. John J.
Xilinx , Inc.
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