Circuit for allowing a two-pass fuse blow to memory chips combin

Details Circuit for allowing a two-pass fuse blow to memory chips combin Circuit for allowing a two-pass fuse blow to memory chips combin

1994-04-04

2000-06-27

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714719, 714720, 714724, 714725, 714819, G11C 2900

Patent

active

060819103

ABSTRACT:
A circuit that enhances the testability of an integrated circuit of a memory type and which identifies defective redundant word lines in a state of the art SRAM macro that combines an ABIST structure with a redundancy mechanism. The circuit allows a two-pass fuse blow after completing the burn-in process that significantly increases the manufacturing yield and repairability of the SRAM macro.

REFERENCES:
patent: 4833652 (1989-05-01), Osobe et al.
patent: 5021944 (1991-06-01), Sasaki et al.
patent: 5173906 (1992-12-01), Dreibelbis et al.
patent: 5299164 (1994-03-01), Takeuchi et al.
"Dynamic Self-Repair Redundancy System" IBM Technical Disclosure Bulletin, vol. 34, H. 5, pp. 448-449, Oct. 1991.

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