Circuit for a read-only memory organized in rows and columns to

Details Circuit for a read-only memory organized in rows and columns to Circuit for a read-only memory organized in rows and columns to

1981-08-06

1984-03-06

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Precharge

365104, 365206, G11C 700

Patent

active

044357893

ABSTRACT:
Circuit arrangement for a read-only memory organized in rows and columns, including bit lines having potentials applied thereto, and selection circuits being connected to the bit lines, being addressed by a bit line decoder and containing at least one selection transistor having a cut-off voltage and a gate potential, for preventing bit line potentials from dropping below a given value at which the selection circuits become conducting without having been selected by the bit line decoder, including current-feed lines each being connected to a different one of the bit lines for feeding current to the bit lines and for ensuring that for each of the selection circuits not selected by the bit line decoder the difference between at least one gate potential of the participating selection transistors and the respective bit line potential is smaller than the cut-off voltage of the respective selection transistors.

REFERENCES:
patent: 4110840 (1978-08-01), Abe et al.
patent: 4185321 (1980-01-01), Iwahashi et al.
patent: 4318014 (1982-03-01), McAlister et al.

Affiliated with

Also associated with

Rating

Circuit for a read-only memory organized in rows and columns to does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit for a read-only memory organized in rows and columns to , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit for a read-only memory organized in rows and columns to will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-744557