Circuit design verification using checkpointing

Details Circuit design verification using checkpointing Circuit design verification using checkpointing

2007-12-11

2007-12-11

Whitmore, Stacy (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C703S013000

Reexamination Certificate

active

11162846

ABSTRACT:
A design verification method, comprising providing a circuit design; creating a stimulus tree diagram for the circuit design, wherein the stimulus tree diagram comprises L stimuli, M checkpointed splits, and N non-checkpointed splits; and executing the stimulus tree diagram, wherein said executing the stimulus tree diagram comprises, for i=1, . . . , M, executing an ithcheckpointed split of the M checkpointed splits, wherein said executing the ithcheckpointed split comprises (a) saving an ithcontext of an ithsimulation environment in which said executing the stimulus tree diagram is performed; and (b) after said saving the ithcontext is performed, executing from the ithcontext along Pi paths of the stimulus tree diagram branching from the ithcheckpointed split, wherein the ithcheckpointed split is a Pi-way split, Pi being an integer greater than 1.

REFERENCES:
patent: 4745355 (1988-05-01), Eichelberger et al.
patent: 5920490 (1999-07-01), Peters
patent: 6363509 (2002-03-01), Parulkar et al.
patent: 6857108 (2005-02-01), Hamlin
patent: 6931611 (2005-08-01), Martin et al.
patent: 7051303 (2006-05-01), Lam et al.
patent: 2003/0061581 (2003-03-01), Baumgartner et al.
patent: 2004/0059977 (2004-03-01), Liau
patent: 2005/0193280 (2005-09-01), Schubert et al.
patent: 2006/0085774 (2006-04-01), Moorby

Affiliated with

Also associated with

Rating

Circuit design verification using checkpointing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit design verification using checkpointing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit design verification using checkpointing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3893822