Circuit configuration for the burn-in test of a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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Reexamination Certificate

active

06581171

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the semiconductor technology field. More specifically, the present invention relates to a circuit configuration of a semiconductor module, to which burn-in test signals from a burn-in test device can be applied.
The failure rate of semiconductor modules as a function of time is known to have a profile which is generally also referred to as “bathtub-shaped”. The profile shape is explained as follows: After a large number of inherently identical semiconductor modules have been completed, a large proportion of these semiconductor modules fails up to a particular time T
1
, so that the failure rate is relatively high. After this time T
1
has been reached, the failure rate remains at a low value until, after the semiconductor modules have been used for a relatively long time, they once more start to fail increasingly from an instant T
2
on.
Hence, in order to prevent semiconductor modules which have just been completed from failing in the possession of the user after a relatively short time, that is to say before the time T
1
has been reached, the manufacturer subjects the semiconductor modules to a burn-in test in which they are artificially aged, so that their “age” is beyond the time T
1
following the burn-in test. The burn-in test is intended to sort out those semiconductor modules which fail after only a short time, so that the user obtains only semiconductor modules which are aged beyond the time T
1
.
In order to age a semiconductor module artificially, a higher voltage is applied to it in the burn-in test. The higher voltage causes the semiconductor module to age artificially relatively quickly, so that the aging process reaches the time T
1
, even though only a short time period has actually elapsed. Moreover, during such a burn-in test, test signals are applied, on the basis of which a functional test of the semiconductor module is carried out and the functionality of the semiconductor module is tested during or after the artificial aging. Functional tests in the context of a burn-in test have the specific object to identify defective functions of the semiconductor module which are caused by individual premature failures.
The receptacles of the test arrangement, so-called burn-in boards, are subject to high temperature requirements and they age relatively quickly. over time this can lead to contact faults at terminals for burn-in test signals and/or burn-in voltages. It has been shown that in burn-in tests in so-called dynamic burn-in test arrangements in which alternating burn-in voltages and test signals are applied to the semiconductor module, the semiconductor modules are not subjected to a burn-in test reliably and correctly, on account of, for example, such contact problems exhibited by the receptacles of the semiconductor modules and the like.
In a prior, commonly assigned development, a semiconductor module for a burn-in test arrangement has been reviewed, in which it was possible to ascertain whether or not the semiconductor module has been in a so-called regulator-off test mode during the burn-in test with regard to the burn-in voltage, for example on account of defective contact connection. Integrated in that semiconductor module there is a component which, when the burn-in voltage is applied, after the burn-in time period has elapsed, has a different characteristic parameter when the regulator is turned off than when the regulator is turned on. The characteristic parameter used in that case is a degradation or deterioration of the component.
If, by way of an example, an address signal as one of the burn-in test signals is affected by a contact fault, this can mean that only a reduced address range of a semiconductor memory to be tested is subjected to a functional test. If the semiconductor memory operates without any faults within this tested address range, this is assessed as a positive test result. Since it has not been customary heretofore to test applied test signals in respect of their freedom from contact faults in such test configurations, it is assumed in such a case that the corresponding semiconductor module has been completely tested and that a situation exists which may be identified as freedom from faults.
For the aforementioned reasons, a burn-in test that has been performed does not lead to the underlying goal whereby exclusively defective semiconductor modules are identified as defective. It can happen, moreover, that defective semiconductor modules are classified as being functional.
SUMMARY OF THE INVENTION
The object of the invention is to provide a burn-in test circuit for a semiconductor component which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which can be used to reliably test whether a complete burn-in test of the semiconductor module has taken place using all of the burn-in test signals that are to be applied to the semiconductor module.
With the above and other objects in view there is provided, in accordance with the invention, a circuit configuration for burn-in testing of a semiconductor module, comprising:
a plurality of memory elements each having an input for receiving and storing therein respective burn-in test signals;
a plurality of terminals for receiving the burn-in test signals from a burn-in test device, the signals having active and inactive states, each of the terminals being connected to an input of the memory elements for storing the respective burn-in test signal present at the terminal;
each of the memory elements having an output outputting an output signal having an active state as soon as an active signal is present at the input of the memory element; and
a functional unit connected to each of the memory elements, the functional unit having an output signal with a first state if all the memory elements output an active state output signal, and with a second state if at least one of the memory elements outputs an inactive state output signal.
In other words, the circuit configuration comprises a memory circuit with memory elements, at least one memory element being assigned to each terminal that receives a burn-in test signal and is connected to that terminal, for storage of the respective burn-in test signal that is present. If an active test signal is present, the corresponding memory element changes to the active state. The memory elements are connected to a functional unit, which, by means of its two states, indicates whether one of the connected memory elements has not changed to the active state. Testing in respect of whether one or a plurality of memory elements have received no active test signal is effected in this way. This indicates that a contact fault is present, if it is presupposed that, for a complete burn-in test, all of the test signals that are to be applied change to the active state at least once. Such information present at the output of the functional unit can be read out during or at the end of a burn-in test and be fed to an evaluation arrangement. The latter establishes whether the quality of the semiconductor module is downgraded or the semiconductor module is subjected to another burn-in test.
If, in a further assumed case, for example, a terminal for a data output of a semiconductor module to be tested is affected by an above-mentioned contact fault, as a consequence a fault-free test result yielded by a functional check cannot be read out. In this case, however, such a test result is assessed as erroneous, whereupon the tested semiconductor module is classified as defective, even though the situation of freedom from faults is inherently present.
In accordance with another feature of the invention, the circuit configuration for burn-in testing further comprises:
a test device for checking a functionality of a semiconductor module;
a memory device connected to the test device for storing test results, the memory device having a first state given the presence of at least one erroneous test result and a second state given a presence of fault-

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