Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2001-11-30
2003-04-29
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S233100, C365S220000
Reexamination Certificate
active
06556486
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a circuit configuration having a memory with an input unit having inputs through which data are fed in parallel and stored in the memory, and an output unit with outputs. The output unit outputs data through the outputs after buffer-storage, and to a method for the synchronization of data that is output through a plurality of data lines in the form of data groups in parallel according to a defined order. The data for each data line is stored in a buffer memory through an input in a storage operation within a time window.
In circuit configurations such as, e.g., memory modules, signals are exchanged in parallel through a plurality of signal lines. During the exchange of the signals, it is necessary, particularly in the case of fast signal transmission methods, to achieve precise synchronization of the signals. In such a case, however, it must be taken into account that the signals on different lines may have propagation times of different lengths. Due to these effects, a common maximum clock frequency is limited because a receiver additionally always requires a minimum of setup time and hold time. In the case of prior art interfaces such as, e.g., Rambus, Synclink, Double Data Rate SDRAMs, etc., clock signals are always concomitantly transmitted in addition to the signals. All of the other control, address, and data signals must be synchronized with these clock signals.
The prior art method is relatively complicated because a separate clock signal has to be transmitted.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration and method for synchronization that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that enables transmission of data in the form of signals without a separate clock signal being transmitted.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a circuit configuration including a buffer memory having memory arrays each with memory cells, an input unit connected to the memory and having inputs through which data is fed in parallel at a given time clock and stored in the memory and input pointers each associated with the memory and each to be controlled by a clock signal, an output unit connected to the memory and having outputs, the output unit outputting data through the outputs after buffer-storage in the memory, and a detection unit connected to the input unit and to the input pointers. Each of the input pointers, under control of the clock signal, is connected to a respective one of the memory arrays for a predetermined time period. Each of the input pointers reads a datum present at one of the inputs into a respective one of the memory cells. Each of the input pointers change, after the predetermined time period has elapsed, to another one of the memory arrays. The detection unit determines, from the data fed in, the given time clock with which the data are fed in. The detection unit feeds to the input pointers the clock signal dependent on the given time clock determined.
One advantage of the invention is that a clock signal is derived from the transmitted data and the signals are stored synchronously with the derived clock signal. As such, precise tuning of the storage time is possible. A precise and short detection time becomes possible as a result.
A further advantage of the invention is that the data are buffer-stored and are output temporally synchronously according to a predetermined order. As such, it is possible to compensate propagation time differences exhibited by the data between a transmitter and the inputs.
Signals that are synchronized according to a common clock signal are available. As a result, the signals can be precisely detected and processed further. Moreover, shorter time windows suffice to be able to detect the signals precisely.
In accordance with another feature of the invention, each of the input pointers has an input, the detection unit is connected to each input of the input pointers, the detection unit determines, for each input of the input pointers, a clock signal with which the data is fed thereto, and the input unit determines, for each of the input pointers, a clock signal derived therefrom and feeds the clock signal to a respective one of the input pointers.
In accordance with a further feature of the invention, the detection unit is connected to the output unit, the detection unit forwards to the output unit a time clock synchronous with the given time clock, and the output unit outputs the data in parallel through the outputs according to the synchronous time clock.
It is advantageous that the detection unit, for each input pointer, determines an individual clock signal and feeds it to the input pointer. The individual clock signal is preferably determined from the data fed through the input of the corresponding input pointer. Very precise control of the input pointers is, thus, possible.
In accordance with an added feature of the invention, the detection unit has a clock input for receiving a second clock signal, the detection unit determines, from the given time clock, a temporally shifted time clock, preferably, lying in a time window defined by the second clock signal, the detection unit passes the shifted time clock to the output unit, and the output unit outputs the data according to the shifted time clock.
The detected time clock is preferably shifted temporally in a manner dependent on a second time clock, so that the signals preferably lie centrally in a predetermined time window. As such, the further processing of the signals is improved, moreover, because the signals that lie centrally in the time window can be detected very precisely. Thus, temporal shifts of the signals on the time axis, which are produced by interfering influences, can be compensated more easily.
In accordance with an additional feature of the invention, the input pointers are respectively connected to one of the inputs, the output unit has an output pointer for each of the outputs; each of the inputs is assigned to a respective one of the outputs, and each of the output pointers respectively outputs the data from the memory arrays at each of the outputs in an order in which the data were written through an assigned one of the inputs.
A respective input of the circuit configuration is assigned to an output and memory arrays are provided between the input and the output, which memory arrays are read in the manner in which the signals were written to the memory arrays. The process ensures that signals are output in the order in which the signals were written. Consequently, a correct order of the signals is ensured despite the buffer-storage.
In accordance with yet another feature of the invention, output pointers are controlled by the time clock that is fed the output unit by the detection unit. Consequently, the output pointers output the data synchronously with the time clock of the detection unit.
In accordance with yet a further feature of the invention, the output unit has an output pointer for each of the outputs, one of the inputs is assigned to a respective one of the outputs through the memory; each output pointer outputs the data from the memory arrays at a respective one of the outputs in an order in which the data was written through each assigned one of the inputs, a controller has output lines connected to the inputs, data is output, from the controller, in parallel in the form of data groups in a first order and according to a first time clock, and the output pointers are synchronized such that, after buffer-storage in the memory, the data is output again through the outputs in the same data groups and in the first order. As such, the data structure of the data is retained despite the buffer-storage.
In accordance with yet an added feature of the invention, the outputs of a circuit unit are preferably connected directly to a processing unit and the processing unit is programmed to pr
Benzinger Herbert
Schneider Ralf
Wirth Norbert
Elms Richard
Locher Ralph E.
Nguyen Tuan T.
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