Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-10-11
2003-12-09
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000, C714S735000
Reexamination Certificate
active
06662326
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for testing circuit cells which can be used for the modular design of a self-test circuit, and to circuit cells having a built-in self-test function. The test method can be used for circuits of modular design.
U.S. Pat. No. 5,422,643 describes a printed circuit board having a plurality of integrated circuits mounted thereon, and a method for testing the integrated circuits mounted on the printed circuit board. In this context, the integrated circuits each have a main circuit unit, test circuits, a latch circuit and a system interface which controls the data input and the data output for the test circuits. The main circuit unit carries out various functions, for example data processing operations. In terms of circuitry, the test circuits are of identical design to the main circuit unit and are connected to the latter and to the system interface by means of a bus in each case.
The paper “Design for Testability—A Survey” in Proceedings of the IEEE, volume 72, No. 1, January 1983, pages 96-112 describes the structure of a BILBO register and its various modes of operation for test pattern generation, signature analysis and test pattern evaluation, and also the operation of the BILBO register as a scan register. Deductive networks are tested using surrounding BILBO registers by operating BILBO registers upstream of the network which is to be tested as a test pattern generator and operating the downstream BILBO register as a signature analysis register.
After production, integrated circuits are subjected to a test method for testing the logic and dynamic responses in order, in the first instance, to detect faulty circuits and, in the second instance, to use the test results to check the performance of the integrated circuits. The integrated circuits comprise a multiplicity of logic components which, for their part, comprise circuit elements and transistors. Circuits with a high level of integration complexity have up to 100,000,000 circuit elements and transistors. In the case of prior art test methods, stimulation test patterns are applied to the integrated circuit by a test machine and response test patterns at the outputs of the integrated circuit are read out by the test machine and compared with a nominal response. The test response pattern output by the circuit which is to be examined (DUT: Device Under Test) needs to match the nominal test response for the integrated circuit to be detected as fault-free.
Integrated circuits are increasingly being designed with BIST structures (BIST: Built-in Self Test), i.e. the integrated circuit additionally implements logic which comprises test pattern generators and test data evaluation modules. In this case, the test machine supplies only one clock signal for the integrated circuit which is to be examined and, on the basis of the data read out from the test, data evaluation modules, determines whether or not the integrated circuit is faulty.
If a self-test function is integrated into the circuit, then the memory unit is replaced by a special memory unit which is able to generate test patterns and to compress test patterns.
In this context, the memory unit in the circuit cell usually comprises a BILBO register (BILBO: Built-In Logic Block Observation). A BILBO register is a register which is independently able to generate test patterns and/or to compress test pattern data. A BILBO register generally has four operating states, namely a normal operating state as a register, an operating state for test pattern generation and test pattern transmission, an operating state for test data reception and test data compression and an operating state as a serial shift register for initialization and reading out/reading in test data.
FIG. 2
shows two interconnected circuit cells in detail during a test run.
The circuit SZ
1
contains a deductive (combinatorial) circuit K
1
for data processing, a memory unit S
1
for storing data, for example a BILBO register, and a memory control unit SSE
1
for controlling the memory unit S
1
. The second memory cell SZ
2
contains a combinatorial circuit K
2
for data processing, a memory unit S
2
for storing data, for example a BILBO register, and a memory control unit SSE
2
for controlling the memory unit S
2
. The memory control units SSE
1
and SSE
2
are respectively connected to the memory units S
1
, S
2
via a plurality of control lines SL
1
and SL
2
. The control lines SL
1
, SL
2
respectively comprise essentially three control lines. The first control line is used to output a test pattern generation instruction from the memory control unit (SSE) to the associated memory unit S. The second control line is used to output a test pattern compression instruction from the memory control unit (SSF) to the memory unit S. The third control line supplies a synchronizing signal from the memory control unit (SSE) to the memory unit S.
In the test mode, a test machine TA controls the local memory control units SSE
1
, SSE
2
in the circuit cells via control lines SL
3
, SL
4
and outputs a synchronizing signal S to the memory control units SSE
1
and SSE
2
via synchronizing signal lines SSL
1
, SSL
2
. In the memory control units SSE
1
, SSE
2
, the synchronizing signal S is switched through to the associated memory unit S
1
, S
2
for synchronization purposes.
A disadvantage of such a test method is that the multiplicity of memory control units SSE need to be connected to the test machine TA via a multiplicity of synchronizing signal lines SSL. The provision of such a clock system, which needs to be provided for test purposes on the integrated circuit which is to be tested, can be achieved only with a very high level of complexity on account of the signal delay time differences. By providing inverter chains having different delay times, the signal synchronizing lines SSL can be designed such that the delay times of the signals to the different memory control units SSE are compensated for. The additional inverter chains, for their part, form additional fault sources and result in a significantly higher power consumption for the integrated circuit.
Synchronous circuits are synchronized by a clock signal which is generated centrally. A synchronous clock signal can be distributed over an integrated circuit only with a very high level of complexity, on account of the signal delay times. In the prior art, this is done, by way of example, using inverter chains with different delay times and driver lines. For this reason, asynchronous circuits are increasingly being used. These can be produced using a modularized circuit design. At the lowest level, the asynchronous circuit of modular design comprises circuit cells which have a combinatorial circuit for data processing, a memory unit and a memory control unit in each case. The memory control units in the circuit cells are connected to the memory control units in further circuit cells via communication lines, and interchange request signals (Request) and reception acknowledgement signals (Acknowledge). Each circuit cell can be operated as a transmission circuit cell on the data output side or as a reception circuit cell on the data input side.
FIG. 1
shows a block diagram of an asynchronous circuit having three circuit cells which can each be connected as transmission or reception circuit cells. The circuit cells are connected to one another via data transmission request lines (R: Request) and data reception acknowledgement lines (A: Acknowledge). In addition, data are transmitted from a transmission circuit cell to a reception standard cell via data lines D for the purpose of further data processing.
SUMMARY OF THE INVENTION
The object of the invention is to provide a test method for circuit cells having a built-in self-test function which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which enables testing to be carried out with a low level of circuit complexity and, in particular, there is no longer a need for a global
Chase Shelly A
De'cady Albert
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
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