Circuit cell for test pattern generation and test pattern...

Details Circuit cell for test pattern generation and test pattern... Circuit cell for test pattern generation and test pattern...

2005-06-28

2005-06-28

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000, C324S073100

Reexamination Certificate

active

06912681

ABSTRACT:
A circuit for test pattern generation compression of circuits with a built-in self-test function has a test data coupling circuit having a test data input for receiving a test data input signal from a circuit cell connected upstream, which signal can be stored in a test data buffer store, a data input for applying a data input signal, which can be stored in a buffer store, a test data output for outputting the buffer-stored test data signal, and a data output for outputting the buffer-stored data signal to a data signal path via a data signal output of the circuit cell, the two buffer stores of the test data coupling circuit having a common feedback signal path, via which the received test data input signal can be coupled into the data signal path depending on a first control signal applied to the test data coupling circuit.

REFERENCES:
patent: 4740970 (1988-04-01), Burrows et al.
patent: 5083049 (1992-01-01), Kagey
patent: 5602855 (1997-02-01), Whetsel, Jr.
patent: 6223312 (2001-04-01), Nozuyama
patent: 6237122 (2001-05-01), Maki
patent: 6662326 (2003-12-01), Schober
patent: 42 21 435 (1994-05-01), None

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